Latch Not clear, While Removing Osc. Probe...!!!

[nithinmoncy]

im working with D latch (SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR) SN74LVC1G175

while probing in scope the Latch works fine !:-D
But, when i removing the Osc. Scope Probe from CLK, The o/p (Q) is not falling down (remains HIGH), while RESET.:-(
also added Load capacitance and resistor to match the impedence as suggested in Datasheet, still problem remains.

any ideas, Pls...

Thanks in Advance..

 

[barry]

1) You don't need any load on the output-that stuff shown on the data sheet is just shown so you know the test conditions they use when they characterize the part
2) There's something else wrong. What is connected to the clock input? What's the voltage on the VCC pin? The Clear pin?

 

[nithinmoncy]

1) You don't need any load on the output-that stuff shown on the data sheet is just shown so you know the test conditions they use when they characterize the part
2) There's something else wrong. What is connected to the clock input? What's the voltage on the VCC pin? The Clear pin?

HI Barry,

1). ok..
2)Clk Input with amplitude of 5V, with ~1.95 to 3 Hz signal | Vcc = 5V | CLR Pin = Triggering Low to Clear the Latch

Thanks!

 

[barry]

Hopefully the clock is a square-wave, right? This device has a maximum rise/fall time on the inputs of 10nS/V; if your input changes too slowly you can damage the part. (And it sounds like you MIGHT have a defective part). And when you say "Amplitude 5V" you mean 0-5V, NOT +/- 2.5V, right?