Large macro cell timing and power characteriztion

[thenonbornking]

Hi all, I am trying to generate the .lib file (timing and power characterization) for a large full-custom macro cell. I plan to use the macro in Cadence Encounter.

Is there a tool for automatically generating the .lib file from an extracted spice netlist?

The spice netlist for the full module is very large. In fact, spice cannot simulate the entire thing. We have had to simulate small parts of the circuit individually and then combine the information together to get first-order timing estimations.

I have looked into SignalStorm Library Characterizer but it seems to be focused on standard cells, which are much smaller than the large module I am working with.

FYI, the module is a 4-ported register file. We don't have a memory-compiler capable of generating 4-ported memories, so we have done a custom layout.

Any suggestions would be appreciated.
Thanks!

 

[thenonbornking]

I have found some more information. It appears that the .lib format is the Synopsys liberty library format. I found a guide on edaboard that gives a simple tutorial for characterizing a simple inverter. However, I am still no closer to finding out how to characterize a larger cell.

I am looking at an example from the memory compiler the foundry gave us. I believe I understand how the timing characteristics are generated. The most confusing thing for me now is how the power characterization is performed. How can I get power information on a per-pin basis? The memory compiler-generated file has power information on the clock pin for three cases:
cen = chip enable
wen = write enable (these are active-low signals
1. !cen & !wen
2. !cen & wen
3. cen

Why is there power when the chip enable is off? Is this leakage?

 

[basudev.dash]

Hello All,

I work in tha same field. There are couple of tools available in the market which can deliver you a timing model out of flat extracted netlist with a complete transister level STA report and timing arcs in the liberty file. But non of them delivers a power characterization data. I have used these tools to generate timing models for for all technology nodes (till 28nm) for a larger macro up to couple of milion transistors. It delivers NLDM, ETM and CCS models as expected. I am looking for some more information on Power characterization. Is there any one know some tool which do the same? I know "PrimeRail" from Synopsys ment for power modelling but it is only restricted to standar cell based degital design. I am looking for some solution for Analog/Mixed signal Macros. If any tool is available, what kind of power info it provieds (static or dynamic power)?

I have found some more information. It appears that the .lib format is the Synopsys liberty library format. I found a guide on edaboard that gives a simple tutorial for characterizing a simple inverter. However, I am still no closer to finding out how to characterize a larger cell.

I am looking at an example from the memory compiler the foundry gave us. I believe I understand how the timing characteristics are generated. The most confusing thing for me now is how the power characterization is performed. How can I get power information on a per-pin basis? The memory compiler-generated file has power information on the clock pin for three cases:
cen = chip enable
wen = write enable (these are active-low signals
1. !cen & !wen
2. !cen & wen
3. cen

Why is there power when the chip enable is off? Is this leakage?