If you use the "single cycle timed loop" the speed is only limited by the FPGA chip. If you describe the same logic in VHDL/Verilog and in LabView FPGA, they should have the same performance.
@std_match,
I am sorry but i didn't understand what you said.. In fact, I don't use the "single cycle timed loop" , i just do a simple code of addition: two input and one output with the additionnal but i didn't know how to determine the execution time.