CAn u be specific..what kind of ADC is it...is it a pipeline ADC or Flash ADC?
For now my point of view is inside ADC architecture got digital error correction inside...mostly also got DAC inside...so this follows the DAC architecture and the SAmple and Hold Circuit.
Most circuit used R2R Laddder for DAC and C2c architecnture for S&H. In this architechture the systems works fine in even number of bits.
I have a different view for the above question....
In some architecture odd no of bits are possible (like simple flash, 2step flash, Folding-Interpolating etc.).....even some times while doing the design....people may find that the resolution coming is 7bit or 9 bit...but they specify one bit lower ...with better spec.....
What I think is that...ultimately the ADC op is processed in digital domain....where, may be, a even no is preferred....but I am not too convinced with the argue....and cannt find any other.....may be someone from industry could answear it better.....
sankudey
From a technical point of view, there is no limitation to make ADCs with an odd number of bits. But, in fact, ADCs of 6, 8, 10 12, 14 ... bits are much more common in the industry.