Kindly explain some queries in Verilog Code

[moonnightingale]

I am stuck with these two statements. Why book has used them. Kindly explain me
As far as always@(clock) or always@(posedge clock) that i understand but i am confused with these.Plz help me

 

[Sink0]

Whats the difference of always@(clock) and always@(code)? Both are inputs... The always is going to be trigged when its argument changes or the logic result of the argument changes... If you have something as always@(clock or code), that means that the always is will be trigged when clock or code changes...

 

[permute]

I am stuck with these two statements. Why book has used them. Kindly explain me
As far as always@(clock) or always@(posedge clock) that i understand but i am confused with these.Plz help me

Its a simulator-related issue nowdays. in verilog/vhdl, a change to a signal(reg/wire) will force the simulator to start looking for how this will change the design. The always @ (conditions) is a way to tell the simulator that this code is/is-not affected by the change/event on the signal. The simulator then evaluates all of the always blocks/assigns that the change to this signal would cause. in most cases, it is only after the evaluation of all blocks that the other signals are actually updated.

If you fail to include the signals in the "sensitivity list" is can infer a latch. but some synthesizers will just ignore the sensitivity list, which means the method can't be used to describe a latch in all cases.

systemverilog is adding some new constructs that allow the user to define the always block as combinatorial, and the tools will fill in the sensitivity list.

 

[moonnightingale]

Thanks a lot for ur replies