KEYPAD Scanner 4x4 cpld

[jokester4u]

I just try to write a program which detect the 4x4 keypad and decode. I try to learn xilinx application xapp512__verilog.zip, but I still confuse how to write this program.

 

[andre_luis]

The model of the reading of a keyboard based on a matrix scanning is a legacy of the times when the number of ports available on chips was much smaller if compared to the current ones. In your case in particular on what you want to scan 16 keys, and would use 8 ports, it wouldn´t be more convenient to read directly all the pins one by one ?

I´m basing on the fact that this application is not complicated, and you can probably find many implementations on the Web or even here, and a simplest solution would bring to you the same result.

 

[jokester4u]

i have got this code on the web but its just 3x4 matrix well i need 4x4 matrix

module keypadscan(reset, 
                  clk, 
                  row, 
                  column, 
                  out);
   // program for 4x3 keypad
   input  reset, clk;
   output [3:0] row; 
   input  [2:0] column; //pullup to vcc 
   output [3:0] out;    //decoded output

   reg  [3:0]  row;
   reg  [3:0]  out;

   wire        scan_en = &column;
   
   //scanning keypad
   always @(posedge clk or posedge reset)
     if (reset) 
       row <= 4'b1110;
     else if (scan_en)
       row <= {row[2:0], row[3]};
   
               
   always @(row or column) begin
      out = 4'b0000;
      case ({row,column})
        7'b1110_110 : out = 4'b0001;
        7'b1110_101 : out = 4'b0010;
        7'b1110_011 : out = 4'b0011;
        
        7'b1101_110 : out = 4'b0100;
        7'b1101_101 : out = 4'b0101;
        7'b1101_011 : out = 4'b0110;
        
        7'b1011_110 : out = 4'b0111;
        7'b1011_101 : out = 4'b1000;
        7'b1011_011 : out = 4'b1001;
        
        7'b0111_110 : out = 4'b1110; // decode as E
        7'b0111_101 : out = 4'b0000;
        7'b0111_011 : out = 4'b1111; // decode as F
      endcase // case({row,column})
   end // always @ (row or column)
endmodule // keypadscan

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still this one is giving an error ??

 

[andre_luis]

As a first attempt, had you even tried to expand the size of variable column on the code above, and also performed some simulation ?

 

[jokester4u]

As a first attempt, had you even tried to expand the size of variable column on the code above, and also performed some simulation ?

I dont even know how to test it on test bench

 

[mrflibble]

I dont even know how to test it on test bench

In which case this should get you started: https://www.asic-world.com/verilog/art_testbench_writing.html