Keep getting warnings that I/O is never used

[jjplaw]

Hi,



I'm trying to synthesize my code which is a hardware wrapper between two other VHDL source codes but I keep getting the following warning:

Input /Output<input/output_name> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

I believe it is caused by the way i coded my processes. One example is shown below. The full source code can be downloaded here
**broken link removed**

process (DMA_SEL,DMA_RENi,DMA_WENi,clk)
begin
if DMA_SEL = x"0" then
input_1_en <= DMA_RENi;
else input_1_en <= 'Z';
end if;

if DMA_SEL = x"1" then
input_2_en <= DMA_RENi;
else input_2_en <= 'Z';
end if;

if DMA_SEL = x"2" then
input_3_en <= DMA_RENi;
else input_3_en <= 'Z';
end if;

if DMA_SEL = x"0" then
output_1_en <= DMA_WENi;
else output_1_en <= 'Z';
end if;

if DMA_SEL = x"1" then
output_2_en <= DMA_WENi;
else output_2_en <= 'Z';
end if;
end process;

I've tried seperating all the if-endif into different process but it still showed the same issue.

Can someone guide me on how should i solve this issue?

The hardware wrapper connects a DMA controller and a component with 3 inputs and 2 outputs. The DMA controller will read or write into the I/Os from/to a inout bus depending on the DMA channel selected and DMA direction.

DMA channel 0 - input 1, output 1
DMA channel 1 - input 2, output 2
DMA channel 2 - input 3

 

[shanmugaveld]

Hi,
If u bring any port in to a module(input) and if u are not used inside that module u will get these warnings.

ex
a: in std_logic;
b: in std_logic;
cut std_logic;

c<= b;

here "a" is not used so u will get above warnings..

Remove port a then u can avoid the warning