jitter in high speed logic gates

[take_care11]

How can I simulate the jitter at the output of an CMOS delay chain due to thermal noise (assume that I have the level 3 spice model of the transistors)?

Any clues?

 

[flatulent]

crude way

This is very crude, but you could put voltage sources in series with each gate output an have them be a sum of very small sine waves of different frequencies.