JFET (lower VD as VG) - simulating a circuit in PSPICE

[pulec]

bf245a how it

Hello,
I´m simulating a circuit in PSPICE, where´s VD lower as VG on the JFET transistor BF245A. I don´t know, where´s the problem... :-( Could you help me? Thank you!

Here´s my schematics and cicrcuit file: **broken link removed**

 

[FvM]

jfet ac analysis

You didn't tell a problem.

P.S.: I reviewed the circuit and actually don't see a problem. It's supposed to work, although there's room for improvements.

To see the circuit in operation, you can feed sine voltages of different level to the input in transient analysis.

 

[pulec]

jfet ac sample problem

This is my terminal work to school. So the circuit is connected correctly? Because the signal must be higher at output as at input... Or I´m in the wrong? Thanks

 

[FvM]

bf245a audio

Please tell, which simulation results are unexpected.

 

[pulec]

jfet.lib

For example AC analysis for V(12)... The voltage is very low (pV)...

 

[FvM]

JFET (lower VD as VG)

O.K., I checked the .OP analysis and found, that the supply voltage are reversed. Why don't you simply check some analysis results yourself?

P.S.: For a meaninful analysis of dynamic behaviour and e.g. fourier analysis, you have to add a sine source.

And there are more errors: M means milliohm for resistors, you have to write MEG for Megohm. Also when the supply ist connected according to the schematic, it's reversed at the OP.

Finally, in transient analysis, you must allow a considerable time for the operation point of the amplitude control circuit to recover from power on, or use .IC statements in analysis.

 

[pulec]

Re: JFET (lower VD as VG)

Hello FvM,
I´ve corrected a errors in a circuit, but the analyses are still bad... Output voltage in AC is still low and Transient displays constant behaviour...
Here´s corrected .cir file:

*
*
V1zdroj 14 0 15V
V2zdroj 15 0 -15V
Vinzdroj 1 0 AC 10mV sin 0 10mv 100HZ
*
*
R1 2 0 1MEG;
R2 3 0 1.5k;
R3 14 4 5.6k;
R4 5 6 100k;
R5 13 9 1MEG;
R6 9 0 1MEG;
R7 14 10 2.2MEG;
R8 7 8 10k;
R9 8 12 1MEG;
R10 10 11 10k;
C1 1 2 100n;
C2 4 5 100n;
C3 3 0 47u;
C4 9 0 10u;
C5 6 7 100n;
C6 11 12 100n;
JT1 4 2 3 BF245A;
JT2 6 13 14 BF245A;
QT3 9 10 14 BC557A;
X1 0 8 15 14 12 LM358;
*
.lib jfet.lib
.lib ebipolar.lib
.lib opamp.lib
*
*
*.DC LIN V1zdroj 30V -15V 1V
.AC LIN 10k 1 100k
*.FOUR 100 V(12)
.tran 100u 100m
.OP
.probe
.end

Could you help me yet? Eventually correct my .cir file a send me this one...
THANK YOU!

 

[FvM]

Re: JFET (lower VD as VG)

It's been said.

Also when the supply ist connected according to the schematic, it's reversed at the OP.

You have to correct the OP supply connections.

X1 0 8 14 15 12 LM358;

 

[pulec]

Re: JFET (lower VD as VG)

Thank you, I got it right.
And could you help me, what kind of circuit is it?

 

[FvM]

JFET (lower VD as VG)

You mean the circuit's overall function? It's an ALC (automatic level control) circuit, as used e.g. for audio recording.
It reduces the gain to keep the output level below a defined limit value. The second FET is used as a variable resistor
to achieve the gain variation.

 

[pulec]

Re: JFET (lower VD as VG)

And how can I do to step change of amplitude? Initial amplitude is 10mV, and I have to do step change to 50mV and to 2 mV at 100Hz frequency.. Thanks...

 

[FvM]

JFET (lower VD as VG)

An analog multiplier supplied with a suitable envelope waveform (sum of pulse sources or PWL source) or time controlled switches with a resistive divider should do.

 

[pulec]

Re: JFET (lower VD as VG)

Could you write me a concrete command(s) for my step change writing above? Thank you.

 

[pulec]

Re: JFET (lower VD as VG)

Sorry, this simple problem is solved, but I have a major problem... I hope, that´s last... At fourier analysis, there is 48 mV voltage with 0 Hz frequency... Why? Thanks.

My .cir file:

*
*
V1zdroj 14 0 15V
V2zdroj 15 0 -15V
Vinzdroj 1 0 AC 10mV sin 1 1mv 100HZ
*Vinzdroj 1 0 PWL (0m,10m)(10m,50m)(20m,10m)(30m,2m)(40m,10m);
*
*
R1 2 0 1MEG;
R2 3 0 1.5k;
R3 14 4 5.6k;
R4 5 6 100k;
R5 13 9 1MEG;
R6 9 0 1MEG;
R7 14 10 2.2MEG;
R8 7 8 10k;
R9 8 12 1MEG;
R10 10 11 10k;
C1 1 2 100n;
C2 4 5 100n;
C3 3 0 47u;
C4 9 0 10u;
C5 6 7 100n;
C6 11 12 100n;
JT1 4 2 3 BF245A;
JT2 6 13 14 BF245A;
QT3 9 10 14 BC557A;
X1 0 8 14 15 12 LM358;
*
.lib jfet.lib
.lib ebipolar.lib
.lib opamp.lib
*
*
.DC LIN V1zdroj 30V -15V 1V
.AC LIN 50 1 500k
.FOUR 100 V(12)
.tran 100u 100m
.OP
.probe
.end

 

[FvM]

JFET (lower VD as VG)

0 Hz is DC component. Why do you worry about it?

 

[pulec]

Re: JFET (lower VD as VG)

But there must be 0 V voltage at 0 HZ frequency (fourier), or 0 V voltage at 0 ms time (transient) because it´s start of analysis... There´s 48 mV (fourier) and -40 mV (transient)... Why? Thanks.

Added after 5 hours 8 minutes:

Hallooo, could anybody help me?

 

[pulec]

Re: JFET (lower VD as VG)

The work is completed, BIG THANKS to FvM, he really helped me But here´s last question: What I need to do, so that at 0 Hz frequency be impulse (voltage) 0 V at fourier analysis..? Here´s a picture, there´s the voltage 48 mV at 0 Hz frequency (I need 0 V voltage...):

**broken link removed**

Thanks!

 

[FvM]

JFET (lower VD as VG)

Unfortunately, I don't understand, why you see a problem with a DC offset in the fourier analysis. It's simply caused by your analysis setup. The circuit output is AC coupled, thus the DC offset surely will disappear after the operating point has stabilized. But you perform a fourier analysis starting at t=0, so the operating point has not stabilized. You hopefully understand the problem, when you look at the transient analysis result in time domain.

As far as I see, everything is normal operation. You can start the data acquisition in transient analysis after a sufficient delay to suppress transient components in result.