The sentence is incomplete, but I believe that the gate's bias must be set with a voltage divider such that at idling the drain voltage (of a JFET connected as common source amplifier, thus its output is the drain) is equal to half the total supply voltage.
But a Jfet is a depletion FET, its gate needs to be below its source voltage so a voltage divider is needed at the source, not at the gate. A single source resistor to ground will bias it and the gate can be at 0VDC. The source resistor can have a parallel bypass capacitor to increase the AC voltage gain.
want to design voltage divider JFET common source amplifier using load line analysis and the output voltage should be biased at the half of supply voltage.
Given:- Power supply = 15V, Power consumption < 5mw , voltage across drain and source = 7.5V
JFET device specification:- Idss = 12mA, Vgs(off) = -3V