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' Iteration limit 10000 is reached ' simulation error

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Advanced Member level 1
Feb 27, 2012
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Jeonju, South Korea
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Dear all,

I am aware of the iteration limit reach error (I guess).

Iteration limit 10000 is reached
Usually it occurs when we have the combinational feedback, but I am actually implementing state machine where
I think that the state and its condition at which my simulator stops will pass by as the clocks proceed in real world...

Can this happen or the simulation error will also cause fatal effect in real circuits as well. As I cannot see any way to change since
in that case I think the state machine will not be same as I want it to be.

Well actually in first place I think this should at all occur, since please see the last line of the following code 'fetch_start <= '0' ;
and hence it should return to elsif condition in the next run of the combinational process,(see below)
process(pr_state, nxt_state, rd_en, fetch_start,empty_sig(0), empty_sig(1))

but since no element in the sensitivity list changes hence the simulation time does not proceed in this combinational block....
What to do, I have put all the relevant elements in the sensitivity list

NOTE: The whole code runs only 2 or three clock cycles after RESET is de-asserted...

case pr_state is
when no_read =>
if(fetch_start /= '0' and fetch_start /= '1') then
fetch_start <= '0';
nxt_state <= read_0;
elsif(fetch_start = '0') then
if(empty_sig(0) = '0') then
rd_enf(0) <= rd_en; rd_enf(1) <= '0';
fetch_start <= '1';
nxt_state <= read_0;
else --if fifo1 empty
rd_enf(1) <= rd_en; rd_enf(0) <= '0' ;
nxt_state <= read_0;
end if;
else nxt_state <= no_read;
fetch_start <= '0';
end if;

Last edited:

Well the problem is with fetch_start. You check it and assign it in the same process. So you have a combinatorial feedback. I suggest registering fetch start.
Thank you for prompt reply... I was actually waiting desperately...

So I should put it the register way, will it comply with the proper state logic, (although it is just a controlling parameter, not actual output that I want).
pardon me for sooo silly question, but this state-machine thing has make me crazy in this case.

- - - Updated - - -

great...seems to be working...thanks again...
of course has to check overall result

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