it seems synpify ignores my false path constraints

[buenos]

hi

it seems synpify ignores my false path constraints.

i set up false paths:

# Clock to Clock
#
define_clock_delay  -rise {fpga_pciclk} -rise {Inst_businterfaces.ldt_clk} -false
define_clock_delay  -fall {x32_clk_better} -rise {x2510_clk8} -false
define_clock_delay  -rise {x32_clk_better} -rise {x2510_clk8} -false
define_clock_delay  -fall {x32_clk_better} -rise {x66mclk} -false
define_clock_delay  -rise {x32_clk_better} -rise {x66mclk} -false
define_clock_delay  -fall {x32_clk_better} -rise {fpga_pciclk} -false
define_clock_delay  -rise {x32_clk_better} -fall {x2510_clk8} -false
define_clock_delay  -fall {x32_clk_better} -fall {x2510_clk8} -false
define_clock_delay  -fall {x32_clk_better} -fall {x66mclk} -false
define_clock_delay  -rise {x32_clk_better} -fall {x66mclk} -false
define_clock_delay  -rise {x32_clk_better} -rise {fpga_pciclk} -false

# Delay Paths
#
define_false_path  -through {ldt_mode} 
define_false_path  -from {{i:Inst_businterfaces.ldt_csr_reg[7:0]}}  -to {{i:Inst_businterfaces.ldt_reg}} 
define_multicycle_path  -through {Inst_lpc_interface.downstream_match}  2
define_false_path  -through {fpgareset_n} 
define_false_path  -from {{i:x32k_clk_better}}  -to {{p:x66mclk}} 
define_false_path  -from {{i:x32k_clk_better}}  -to {{i:*2510*}} 
define_false_path  -from {{i:fpgareset_n}}  -to {{i:*}} 
define_false_path  -through {fp_switch_db_n}

the point is that fpgareset_n is synchronised to x32_clk_better, and that is asynchronous to the other circuits, driven by the x66mclk, fpga_pciclk and x2510_clk8.
I keep getting timing violations on paths going through fpgareset_n

what constraint should I set up to disable timing checks on these paths?
because it seems my constraints are not effective.

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