vhdl generic mux
First of all, code 1 is not a MUX, but rather a multi-input OR gate.
A MUX will have a number of input and an output, plus a selector (which select which of the input goes to the output). An example is a 4-to-1 mux, which have 4 inputs, 1 output, and 2 select lines (which can take the value of 00, 01, 10 or 11 and select which input goes to the output).
The 2nd piece of code will not synthesize because a for loop is not synthesizable. As I written in another thread:
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There is a mistake that many people do when begining to program for FPGA, especially if those people previously programmed structured language like 'C'.
You have to think, throughout your design, that you're implementing hardware functions, and not a sequential program. You have to keep in mind that everything happen in parallel. For example, you can not synthesize a for loop. A for loop is a sequential thing. This is good for simulating (testbenching) only. So, to design something that work like a for loop, you have to synthesize a counter, and do different things depending on the output. The counter become one entity, and the actions (logic blocks) depending on the counter output is another entity.
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Here, if you wish to design a multi-input OR gate, with width parameterizable, a way to do it would be
`define NB_WB_DEVICES 3
wire wb_ack_i;
wire [`NB_WB_DEVICES-1:0] wb_ack_i_mux;
assign wb_ack_i = |wb_ack_i_mux[`NB_WB_DEVICES-1:0];
Note the pipe character ('|', OR) before the wb_ack_i_mux in the above line.
The unary pipe character '|' defined before an identifier is a bit-to-bit OR, meaning that it will take all bits in wb_ack_i_mux[`NB_WB_DEVICES-1:0] and OR it togetter, giving a 1-bit result.