module narrow_pulse
(
input clk,
output reg out_pulse //
);
parameter delay = 1,
width = 3;
reg [delay:0] pulse_del /* synthesis syn_keep */;
reg [width:0] pulse_wdh /* synthesis syn_keep */;
integer i;
always @(*)
begin
pulse_del[0] <= clk;
for ( i=1; i <= delay; i = i + 1)
pulse_del[i] <= pulse_del[i-1];
end
always @(*)
begin
pulse_wdh[0] <= out_pulse;
for ( i=1; i <= width; i = i + 1)
pulse_wdh[i] <= pulse_wdh[i-1];
end
wire pulse_reset = pulse_wdh[width];
wire pulse_clk = pulse_del[delay];
always @(posedge pulse_clk or posedge pulse_reset)
if ( pulse_reset ) out_pulse <= 0;
else out_pulse <= 1'b1;
endmodule