Issues in using xilinx primitives to generate delay elements

[vidyaredy]

xilinx delay cell

Hi friends,

In my design I will be delaying one signal(clock) to generate other signals. I have used xilinx primitives buffer(buf or bufg) to generate delay elements. When I synthesize this individually it gives 7.266ns combinational path delay. when I instantiated this in top module 15 times its generating the same delay......... :-( . Also sythesis report says the destination library for buf or bufg has different definition the model has been changed to buf1 or bufg1. when I simulated in modelsim all outputs are happenning on the same edge even though the design is not synchronised with clock. I am not able to see delay in signals at all.....plz let me know if u have any idea.

 

[mmarco76]

xilinx add delay

You need to change your approach, a design based on delay is very bad one expecially if it's the clock that you wanna delay.
What you do is not correct and the syntethizer remove it (that's the reason why you'll be given the same delay no matter how many buffer you insert).

The only reliable way to generate a clock delayed by one with a Xilinx should be use a DLL.

Just to let you know, try to think about a synchronous system to do what you want if you really want to still develop FPGA else you'll encounter very unpredictable problems.

 

[FvM]

xilinx delay

Although they're far from recommended synchronous FPGA design, logic cell delay chains may be useful sometimes. To prevent the synthesis tool from simply removing this (in it's view) redundant logic cells, specific synthesis attributes or constraints are necessary. You should check the Xilinx ISE documentation, which synthesis attributes are provided for this purpose.

Altera discusses the implementation of ring oscillators from logic cell chains for cryptographic purposes, see chapter 13 of the Advanced Synthesis Cookbook:https://www.altera.com/literature/manual/stx_cookbook.pdf

 

[vidyaredy]

synthesize delay in xilinx

I really did not understand from this topic which u asked me to read ie., Random and Pseudorandom Functions from altera cook book. I need to generate very narrow pluse on every clock cycle, I cant use counter. Is there any another way?

 

[FvM]

xilinx how buf clk

I was referring to techniques that use logic cell delays. The said example is about ring oscillators, but pulse delays can be implemented the same way.

Did you understand in the meantime, why your design doesn't work? That's actually the basic point in my post. The ring oscillator example should be only a supplement, also documenting that a FPGA vendor sometimes suggests dirty tricks far apart from The only reliable way.

 

[j_andr]

delay chain xilinx

I need to generate very narrow pluse on every clock cycle

if this is your goal, may be this example will help ?

module narrow_pulse
(
  input      clk,
  output reg out_pulse  //
);

parameter  delay = 1,
           width = 3;
           
reg [delay:0]  pulse_del /* synthesis syn_keep */;
reg [width:0]  pulse_wdh /* synthesis syn_keep */;

integer i;

always @(*)
   begin
     pulse_del[0] <= clk;
     for ( i=1; i <= delay; i = i + 1)
        pulse_del[i] <= pulse_del[i-1];
   end
   
always @(*)
   begin
     pulse_wdh[0] <= out_pulse;
     for ( i=1; i <= width; i = i + 1)     
        pulse_wdh[i] <= pulse_wdh[i-1];
   end

wire pulse_reset = pulse_wdh[width];
wire pulse_clk   = pulse_del[delay];

always @(posedge pulse_clk or posedge pulse_reset)
   if ( pulse_reset ) out_pulse <= 0;
   else               out_pulse <= 1'b1;

endmodule

the statement: "/* synthesis syn_keep */" prevents compiler from
removing redundant logic;

a schematic view of the code above:



and simulator waves:




--

 

[bibo1978]

xilinx synthesis issues

First of all I wouldn't do such a delay ever, it is inreliable and a Buf object is not routed to the global clock network and you can't use a BUFG to delay a clock, use DCM for delaying a clock

Anyway I think the problem is in the resolution you are using in the modelsim and in the generation of the model, is it clear!

What you are doing is a bad design practice, u have to know is the Post PAR simulation is not what the reality is

 

[j_andr]

delay cell xilinx implementation

I assume bibo you react on my post;
- FvM stated it very clearly: it's not a recommended design style
so I do not see a reason to repeat it;
- vidyaredy did not get the example given by FvM so I showed
an illustrative code;

I wouldn't do such a delay ever, it is inreliable

it produces a short pulse some time after a pos slope of a clock;
if this is all you need - it's very reliable;

Buf object is not routed to the global clock network

buf is not routed, right, but there are no reasons to do it;
the out_pulse should be - eventually - routed via global clock buffer,
if it is supposed to drive many clock inputs;

What you are doing is a bad design practice

right, 99% of designs do not need such 'tricks', but if it's useful
in a particular case - why not ? just 'because not' ?

u have to know the Post PAR simulation is not what the reality is

disagree - my experience with quartus P&R simulations are positive,
very positive;
--

 

[FvM]

xilinx fpga delay cell

I basically agree with j_andr view points. I already expected some well-meant warnings to beware of dirty design practices, thus I quoted an official Altera document, that suggests it anyway. Some additional thoughts of mine:

Logic cell delay lines are very reliable in so far as they generate well defined delays. They have an application e. g. in user logic ring oscillators for random generators. By the way, a dedicated hardware PLL (as a Xilinx DCM) is also build from ring oscillators, but differential ones with variable supply.

A german chip design house holds even patents on digital controlled oscillators based on pure digital logic cell delays:

Also pulse shaping or pulse generation is a possible field of application,as you demonstrated in your example. Logic cell delays also can be used to generate phase shifted or multiplied clocks with small logic devices, that have no PLL.

Newer Altera devices have clock control blocks, that allow to drive global clock networks from logic cells.

An interesting question is, if the FPGA tools would be able to perform a meaningful timing analysis of delay chains fixed by syn_keep attributes.

 

[bibo1978]

xilinx delay function

J_andr I dont say that tricks will not work and it is ok to do so and I have done this actually in some ciruits you can't get some data except with a delayed pulse" like DDR DQs" but you can't get a delayed clock this way and if your pulse route is big or it drives more than one elment you may get.
when I talked about post PAR results truly it is inaccurate there is some extra issues that cant be accounted for in post PAR pluse from my experience (some elements might behave with different ratings) and believe me post PAR is not as accurate as you think if your design frequency requirement is tight you may get issues that aren't in post PAR also post PAR irregualities (your design might work in some cells but its assumetric ones will not work!!) anyway my advice for you is if you have enough time tolerance in your frequency that the delay is relaxed then it is ok your design probably will work right yet if yor constraints are very tight then make sure of your design after all the modelsim is just a digital simulation tool there are many issues out there that are unaccounted for
an assertion tool might be needed sometime with your design if it is very complicated