Nikolai
Member level 3
Firstly i'd like to know the difference between the following modes:
(Im referring to the Xilinx XST userguide)
1.) Read first
2.) Write first
3.) No change..
Secondly, in the following code (No change mode)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rams_03 is
port (clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(5 downto 0);
di : in std_logic_vector(15 downto 0);
do : out std_logic_vector(15 downto 0));
end rams_03;
architecture syn of rams_03 is
type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en = '1' then
if we = '1' then
RAM(conv_integer(addr)) <= di;
else
do <= RAM( conv_integer(addr));
end if;
end if;
end if;
end process;
end syn;
a.) why is ram_type defined as a "signal". wouldnt a "variable" do just fine or mebbe better since there are no delays associated with it.
b.) why are input and output ports seperate. Isnt ram supposed to have a single data bus ? Further will the multiple driver resolution problem arise if i declare the data bus as INOUT.
(Im referring to the Xilinx XST userguide)
1.) Read first
2.) Write first
3.) No change..
Secondly, in the following code (No change mode)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rams_03 is
port (clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(5 downto 0);
di : in std_logic_vector(15 downto 0);
do : out std_logic_vector(15 downto 0));
end rams_03;
architecture syn of rams_03 is
type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en = '1' then
if we = '1' then
RAM(conv_integer(addr)) <= di;
else
do <= RAM( conv_integer(addr));
end if;
end if;
end if;
end process;
end syn;
a.) why is ram_type defined as a "signal". wouldnt a "variable" do just fine or mebbe better since there are no delays associated with it.
b.) why are input and output ports seperate. Isnt ram supposed to have a single data bus ? Further will the multiple driver resolution problem arise if i declare the data bus as INOUT.