kalyansrinivas
Advanced Member level 4
Hi all,
We had a VIRTEX-4 Fpga and a cypress controller(CY7C68013) on our board the reset signal for CYPRESS chip comes from FPGA(VIRTEX-4). The problem we are facing is that for some reason the reset coming from FPGA doesnt enable the cypress chip but when forced externally the chip takes it properly . Do i need to make any settings in XILINX ISE to make the IO driven from FPGA looklike a reset signal passed from external environment
Thankyou in advance
M Kalyansrinivas
We had a VIRTEX-4 Fpga and a cypress controller(CY7C68013) on our board the reset signal for CYPRESS chip comes from FPGA(VIRTEX-4). The problem we are facing is that for some reason the reset coming from FPGA doesnt enable the cypress chip but when forced externally the chip takes it properly . Do i need to make any settings in XILINX ISE to make the IO driven from FPGA looklike a reset signal passed from external environment
Thankyou in advance
M Kalyansrinivas