shaikss
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Hi Folks,
I am working on the design of rectifier. I have attached the reference paper.
Below are my queries:
I have gone through the thesis work( simulated in 130nm) and I observed that the circuit dimensions are as below
M0, M1 are 8um each
M2,M3 are 17.17um each
M4,M5,M6,M7 are 10um each.
M8, M10 are 5u each
M9,M12 are 10um each.
The simulated result of the paper says that efficiency is around 60%. They had achieved 260mV with I stage and 520mV with II second stage, with input being 350mV/4.25uW, and load is 100k ohms.
Now, I have tried to simulate the circuit using 180nm technology. I maintained the same circuit dimensions as mentioned above. I couldn't see reasonable efficiency (Less than 10%). But I could see 30% efficiency for an input voltage of 600mV. And the load resistance is 10k. When I checked current at all nodes, I found that source current (+ve peak) is around 264uA. The output current is 5uA.
Simulated thesis paper results shows that input current is around 12uA. But I could see current in 260uA.
What should I do in order to see good results in my circuit?
I am in desperate need of help. Pls help me.
PS: have attached the reference paper, current plots and schematic.
I am working on the design of rectifier. I have attached the reference paper.
Below are my queries:
I have gone through the thesis work( simulated in 130nm) and I observed that the circuit dimensions are as below
M0, M1 are 8um each
M2,M3 are 17.17um each
M4,M5,M6,M7 are 10um each.
M8, M10 are 5u each
M9,M12 are 10um each.
The simulated result of the paper says that efficiency is around 60%. They had achieved 260mV with I stage and 520mV with II second stage, with input being 350mV/4.25uW, and load is 100k ohms.
Now, I have tried to simulate the circuit using 180nm technology. I maintained the same circuit dimensions as mentioned above. I couldn't see reasonable efficiency (Less than 10%). But I could see 30% efficiency for an input voltage of 600mV. And the load resistance is 10k. When I checked current at all nodes, I found that source current (+ve peak) is around 264uA. The output current is 5uA.
Simulated thesis paper results shows that input current is around 12uA. But I could see current in 260uA.
What should I do in order to see good results in my circuit?
I am in desperate need of help. Pls help me.
PS: have attached the reference paper, current plots and schematic.
