Code dot - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ----------------------------- begin if (clk'event and clk='1') then count <=count+1; if (count = 0) then tmp <= NOT tmp; count <= 0; end if; tmp3 <= NOT tmp3 after 20 ns ; end if; clock_out <= tmp; clock_out3 <= tmp3; end process --------------------------------------
But first and second output in same phase. why "after 20 ns" do not working?
I do not use the simulator. testing on the real device checked outputs with an oscilloscope. it's always different only 1ns.What is the period of clk?
What is your simulator resolution set to?
First, thanks for this information. You are saving a lot time for me.
Second, how to make little latency for second output in ”real life”.
You may use the Xilinx primitive "ODELAY". Using delay tap settings, an i/p signal can be delayed by a desired amount which appears at the o/p of the ODELAY. The Xilinx ISE documentation on ODELAY should have more details.Second, how to make little latency for second output in ”real life”.
Synthesis doesn't care for sensitivity lists although the tool may warn about missing entries.What is the sensitivity list of the process?
If the OP instantiates only 1 ODELAY then yes. It was just an idea to get started.ODELAY is only feasible for sub nanosecond delays, so it's not answering the question how to generate 20 ns delay.
Synthesis doesn't care for sensitivity lists although the tool may warn about missing entries.
Code dot - [expand] 1 2 clock_out <= tmp; clock_out3 <= tmp3;
Code dot - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity Clock_Divider is port ( clk: in std_logic; clock_out: out std_logic; clock_out2: out std_logic); end Clock_Divider; architecture bhv of Clock_Divider is signal count: integer:=0; signal tmp : std_logic := '0'; signal tmp2 : std_logic := '0'; begin process(clk) begin if (clk'event and clk='1') then count <=count+1; if (count = 1) then tmp <= NOT tmp; count <= 0; end if; tmp2 <= NOT tmp2; end if; clock_out <= tmp; clock_out2 <= tmp2; end process; end bhv;
I think it should be MHz (Megahertz) instead of mHz (millihertz).CLK = 45mhz
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity Clock_Divider is port ( clk: in std_logic; clock_out: out std_logic; clock_out2: out std_logic); end Clock_Divider; architecture bhv of Clock_Divider is signal count: integer:=0; signal tmp : std_logic := '0'; signal tmp2 : std_logic := '0'; begin process(clk) begin if (clk'event and clk='1') then count <=count+1; if (count = 1) then tmp <= NOT tmp; count <= 0; end if; clock_out <= tmp; clock_out2 <= clock_out; end if; end process; end bhv;
With that being said, I have no idea how to do it on a XC2C64A.Just realized that the thread is referring to XC264 CPLD, no ODELAY features available at all.
Hi,
I assume you didn´t try the code...(just complain about it?)
What are your results of the code of post#15?
Klaus
With that being said, I have no idea how to do it on a XC2C64A.
If it was a Xilinx 7 series FPGA, the chained IDELAY approach might have helped.
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