Here I am giving the program
My top module is tx_fifo.v
tx_fifo.v
module tx_fifo(din,wr_en,wr_clk,dout,rd_en,rd_clk,full,empty,rst
);
input [7:0] din ;
input wr_en ;
input wr_clk ;
input rst ;
input rd_en ;
input rd_clk ;
output [7:0] dout ;
output full ;
output empty ;
fifo u1 (
.din(din),
.wr_en(wr_en),
.wr_clk(wr_clk),
.rst(rst),
.rd_en(rd_en),
.rd_clk(rd_clk),
.dout(dout),
.full(full),
.empty(empty)
);
endmodule
IP core wrapper file fifo.v is instantiated as u1
fifo.v
module fifo( rd_en, wr_en, full, empty, wr_clk, rst, rd_clk, dout, din
);
input rd_en;
input wr_en;
output full;
output empty;
input wr_clk;
input rst;
input rd_clk;
output [7 : 0] dout;
input [7 : 0] din;
// synthesis translate_off
wire \BU2/U0/grf.rf/mem/tmp_ram_rd_en ;
wire \BU2/N22 ;
wire \BU2/N20 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000118_123 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000093_122 ;
wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or000053_121 ;
.
.
.
.
.
GND \BU2/XST_GND (
.G(\BU2/rd_data_count [0])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire PRLD;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
// synthesis translate_on
Test bench of tx_fifo.v is tx_fifo_test.v
tx_fifo_test.v
module tx_fifo_test;
// Inputs
reg rd_en;
reg wr_en;
reg wr_clk;
reg rst;
reg rd_clk;
reg [7:0] din;
integer i = 0 ;
reg [8:0] stim[31:0] ;
// Outputs
wire full;
wire empty;
wire [7:0] dout;
// Instantiate the Unit Under Test (UUT)
tx_fifo uut (
.rd_en(rd_en),
.wr_en(wr_en),
.full(full),
.empty(empty),
.wr_clk(wr_clk),
.rst(rst),
.rd_clk(rd_clk),
.dout(dout),
.din(din)
);
initial begin
// Initialize Inputs
$readmemh("input.vec",stim);
$display ("stim[0]=%b",stim[0]);
rd_en = 0;
wr_en = 0;
wr_clk = 1;
rst = 1;
rd_clk = 1;
din = 0;
#2 rst = 0;
for (i=0 ; i<20 ; i=i+1)
begin
#2 wr_en = 1 ;
din = stim ;
end
#2 wr_en = 0 ;
#2 rd_en = 1 ;
#2 rd_en = 0 ;
#2 rd_en = 1 ;
#2 rd_en = 0 ;
#2 rd_en = 1 ;
#150 $finish ;
end
always
#1 wr_clk = ~wr_clk ;
always
#1 rd_clk = ~rd_clk ;
endmodule
This is the code.The output waveform is attached.