ISE 9.1i simulaor prob verilog code - help me to solve error

verilog library module instantiation

Hi,

I am getting the following simulaor errors while doing behavioural simulaion using ise simulator on ise9.1i. I am running ise tutorial 8

HDLParsers:3482 - Could not resolve instantiated unit ten_cnt in Verilog module work/stopwatch in any library
ERROR:Simulator:198 - Failed when handling dependencies for module stopwatch

I have copied the stopwatch.v code here, as i could not attach the file.
If u find any modifications in this for the simulaion errors as i mentioned earlier please highlight to me.


////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
//
// Create Date: 10:05:26 01/31/05
// Design Name: Stopwatch
// Module Name: Stopwatch
// Project Name: ISE In Depth Tutorial
// Target Device: xc3s200-4ft256
// Tool versions: ISE 7.1i
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module stopwatch(STRTSTOP, RESET, CLK, SEG_A, SEG_B, SEG_C, SEG_D, SEG_E,
SEG_F, SEG_G, SEG_DP, AN);
input STRTSTOP;
input RESET;
input CLK;
output SEG_A;
output SEG_B;
output SEG_C;
output SEG_D;
output SEG_E;
output SEG_F;
output SEG_G;
output SEG_DP;
output [3:0] AN /* synthesis xc_loc = "e14,f14,g14,d14" */;
//exemplar attribute AN LOC e13,f14,g14,d14
//pragma attribute AN LOC e13,f14,g14,d14
//synthesis attribute LOC of AN is "e13 f14 g14 d14"

wire [6:0] hundredthsout, tenthsout, onesout, tensout, minutesout;
wire [3:0] hex2led_int1, hex2led_int2, hex2led_int3, hex2led_int4, hex2led_int5;
wire clk_262144k, clk_int, clk_100, clk_en_int, rst_int, locked, strtstop_debounced;
wire time_cnt_ce, ten_cnt_ce, ten_cnt_thresh1, ten_cnt_thresh2;

assign ten_cnt_ce = clk_en_int & ten_cnt_thresh1;
assign time_cnt_ce = ten_cnt_thresh2 & ten_cnt_ce;

// Place the Coregen module instantiation for ten_cnt here
ten_cnt ten_cnt1 (
.clk(clk_100),
.ce(clk_en_int),
.ainit(rst_int),
.thresh0(ten_cnt_thresh1),
.q(hex2led_int1)); // Bus [3 : 0]

ten_cnt ten_cnt2 (
.clk(clk_100),
.ce(clk_en_int),
.ainit(rst_int),
.thresh0(ten_cnt_thresh2),
.q(hex2led_int2)); // Bus [3 : 0]


//Insert DCM1 instantiation here
dcm1 instance_name (
.CLKIN_IN(CLK),
.RST_IN(RESET),
.CLKFX_OUT(clk_262144k),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(clk_int),
.LOCKED_OUT(locked)
);

hex2led HEX2LED_1 (
.HEX(hex2led_int1),
.LED(hundredthsout));

hex2led HEX2LED_2 (
.HEX(hex2led_int2),
.LED(tenthsout));

hex2led HEX2LED_3 (
.HEX(hex2led_int3),
.LED(onesout));

hex2led HEX2LED_4 (
.HEX(hex2led_int4),
.LED(tensout));

hex2led HEX2LED_5 (
.HEX(hex2led_int5),
.LED(minutesout));

debounce DEBOUNCE_1 (
.SIG_IN(STRTSTOP),
.CLK(clk_100),
.SIG_OUT(strtstop_debounced));

time_cnt TIMECNT_1 (
.CLK(clk_100),
.CE(time_cnt_ce),
.CLR(rst_int),
.SEC_LSB(hex2led_int3),
.SEC_MSB(hex2led_int4),
.MINUTES(hex2led_int5));

statmach STATEMACH_1 (
.CLK(clk_100),
.reset(RESET),
.DCM_lock(locked),
.strtstop(strtstop_debounced),
.clken(clk_en_int),
.rst(rst_int));

led_control LEDCONTROL_1 (
.CLK(clk_int),
.HUNDREDTHS({hundredthsout,1'b1}),
.TENTHS({tenthsout,1'b1}),
.ONES({onesout,1'b0}),
.TENS({tensout,1'b1}),
.MINUTES({minutesout,1'b0}),
.AN(AN),
.SEVEN_SEG({SEG_G,SEG_F,SEG_E,SEG_D,SEG_C,SEG_B,SEG_A,SEG_DP}));

clk_div_262k CLKDIV262K_1 (
.CLK(clk_262144k),
.DIV_262144(clk_100));

endmodule


------------------`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: Premduth Vidyanandan
//
// Create Date: 15:45:44 02/05/2005
// Design Name: stopwatch
// Module Name: stopwatch_tb.v
// Project Name: ISE In-Depth Tutorial
// Target Device: xc3s200-4ft256
// Tool versions: ISE 7.1i
// Description:
//
// Verilog Test Fixture created by ISE for module: stopwatch
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module stopwatch_tb;

// Inputs
reg STRTSTOP;
reg RESET;
reg CLK;

// Outputs
wire SEG_A;
wire SEG_B;
wire SEG_C;
wire SEG_D;
wire SEG_E;
wire SEG_F;
wire SEG_G;
wire SEG_DP;
wire [3:0] AN;

// Instantiate the Unit Under Test (UUT)
stopwatch uut (
.STRTSTOP(STRTSTOP),
.RESET(RESET),
.CLK(CLK),
.SEG_A(SEG_A),
.SEG_B(SEG_B),
.SEG_C(SEG_C),
.SEG_D(SEG_D),
.SEG_E(SEG_E),
.SEG_F(SEG_F),
.SEG_G(SEG_G),
.SEG_DP(SEG_DP),
.AN(AN)
);

initial begin
// Initialize Inputs
STRTSTOP = 0;
RESET = 1;
CLK = 0;

// Wait 100 ns for global reset to finish
#100;
end
// Add stimulus here
//define clock
always begin
#10 CLK = ~CLK;
end

//Stimulus for RESET and STRTSTOP
initial begin
#150 RESET = 0;
#200 STRTSTOP = 1;
#3000 $finish;
end

endmodule

----------



Thanks

ise reg output verilog

This design appears to using a CoreGen file, "ten_cnt". Your project needs to have this file linked in so that the simulator understands what is inside this 'box'. If I remember correctly, this is a two file process. There should be a Verilog wrapper file for the Verilog linker and a compiled file for the actual simulator.
Search the tutorial directory for all files with the name "ten_cnt". Copy them into your project and add the ten_cnt.v file into the project as a source file. Do a fresh build and I think the error will be gone.