ISE 11.4 EDK & Spartan3E Starter Kit

[headup]

hi! i'm new in EDK, please excuse me if the question is stuped. i have a little problem - i use EDK ISE 11.4 to generate microblaze system with BSB. ok, next step i test_mem project generated by SDK. i run it on target (spartan-3e starter kit, rev D) and ddr test pass successfully, but FLASH test failed in all 8/16/32 bits mode. i can't understand - is this problem in v11.4 ot my board is demaged? if i try to boot fpga from platform flash (base test, by default) - there is no problem. i look in ucf file and some strange constraints are placed for platform flash address bus - in user manual ug230 they are a little different. someone to have this problem too? or the problem is "in my TV"

 

[bigdogguru]

Is the starter kit from Xilinx or Digilent? Beware there are differences in the UCF depending on the manufacture. I have both Xilinx and Digilent Spartan 3E boards and even though Digilent provides a PDF users guide that looks identical to the Xilinx PDF from their website, there are clear differences in the sample UCFs at the end of the PDF. Even components as simple as LEDs have different constraints.

 

[Jack// ani]

Make sure you have selected the right board and version in BSB.

If its UCF issue as bigdogguru said, you can manually cross verify by looking at the datasheet and make the changes accordingly.

 

[headup]

ok, the kit is from digilent. i will verify ucf file from start to end, but peripheral test was passed correctly - leds was blinking, switches are read correctly. tomorrow i will post the results for FLASH. and the other question is: memory controller - address bus 24 is controlled by CPLD. may be i must make some changes here? and the address bus is assigned from upper to lower bits, not from lower to upper bit as i expect.

 

[bigdogguru]

So your using the Digilent Spartan 3E Starter Kit?

Which gate count 500k or 1600k?

Can you zip up the project with the required files, UCF and up load or email them to me?

I have both boards and will try and duplicate the implementation here.
We'll see if it is your board or more likely another issue.

 

[headup]

hi again! @bigdogguru, thank you for support, i realy have no alternatives to test this example on Xilinx board. The kit is this - Digilent Spartan-3E Starter Kit (500K), rev D, and u are right - in EDK i can select Xilinx as manifacurer, but i have no option for Digilent version. Realy i was surpised to understand there are two versions (Dig. and Xil.) of this board with a bit but important differences. this is my example created by SDK (noted with this suffix), and EDK project. I remove documents to get low size of file and i place them in separate rar if u need to see versions of modules.

 

[bigdogguru]

Alright, I assume you received the PM explaining the results. Here is the TestApp_Memory_microblaze_0 implementation for the Digilent/Xilinx Spartan 3E Starter Kit Board! Built from scratch and runs on the same board over here. Attach a straight through, NOT NULL MODEM, serial cable to the DCE port settings 115200-8n1n.

DO NOT UPGRADE project to differect XPS version, download bit file directly to the fpga with Impact (boundary scan),

You should see the following on hyperterminal:

-- Entering main() --
Starting MemoryTest for DDR_SDRAM:
Running 32-bit test...PASSED!
Running 16-bit test...PASSED!
Running 8-bit test...PASSED!
-- Exiting main() --

Let me know the results. I hope it works.

 

[bigdogguru]

P.S. Remember to configure all jumpers as shown in the photo in the above reply, except remove M0 and M2 jumpers leaving only M1. This of course boot the code loaded directly in the fpga, boundary scan.

 

[headup]

bigdogguru, i'm sorry for my mistaske - i was first read your PM and later the forum. but my questions in pm are valid DDR is not the problem - the DDR test pass in all modes. The problem is FLASH:

ddr test pass successfully, but FLASH test failed in all 8/16/32 bits mode

Can you regenerate project with flash test enabled?

 

[bigdogguru]

Ok,

But I still want you to download the bit file and let me know if the implementation runs correctly, you see the output as shown above. To answer your question, Impact 11.4 doesn't know or care who compiled the bit file. Configure your board as shown in the photo, but leave M0 and M2 off, download the bit file directly to the FPGA.

Let me know what happens!

Added after 2 hours 50 minutes:

The reason I want you to still download the above bit file is to ensure that we have the same model and rev of the board.

Neither of the applications you included in the last zipped project file tested any of the flash. I have attached a project with SPI Flash test, download the "download.bit" in the implementation folder directly using Impact and the same serial port, cable and hyperterminal configuration. If successful you will see:

Serial Flash Test
Manufacturer Code = : 20
Memory Type = : 20
Memory Capacity = : 15
M25P16 = 20, 20, 15

Chip Erase Starting
Chip Erase Complete - verifying
Erase verified

Data being written
Test Data Written; reading back

Flash Test PASSED!

Hope it flies on your board!