So I am asking if I am very good at VHDL and know nothing about Verilog , will I need a lot of time and effort to learn Verilog or will it be a smooth drill to do ?
Verilog syntactically has many similarities to that of the C programming language. Therefore, if you are familiar with the C programming language many of the structures and other syntax of Verilog can be easily learned.
However, it should be remembered, just as VHDL is concurrent hardware design language, so is Verilog. Do not fall into the common trap of assuming the program execution flow of the C language and the concurrent characteristics of Verilog are similar, they are not.
You might find the Verilog HDL Group of interest.
Also the following texts as introductions to Verilog are quite good:
The following text takes a more practical approach to Verilog, concentrating on synthesizable aspects.