saturation region of transistor
Making sure that VDS>VGS-Vt is not a very good idea, because this relation is only (roughly) valid when the transistor is operating in strong inversion.
It may happen that VGS<Vt (there is still current - sub-threshold operation) and this does NOT mean that you can have a zero (or negative ...) VDS and still have the MOS in saturation.
I don't know exactly what simulator you are using. In HSPICE, for example, there is an indication of VDS and VDSsat. To have the transistor in saturation you must have VDS>VDSsat (with some margin, like 100 mV or so).
Another possibility is to compare the 'gm' and 'gds' of the transistor. When you are in saturation, the drain current is mostly defined by the VGS and the influence from the variations on VDS should be small. You should have gm (which relates the drain current variations with vgs variations) >> gds (which relates the drain current variations with vds variations).
Regards