Is this W/L feasible?

[ananthesh bhat]

Hello all,

When I was designing a circuit, after satisfying the spec, I'm getting a W/L ratio for one transistor as 3500. Is this ok? Can I go ahead or should I change the design?

This is in 350nm PDK.

 

[Dominik Przyborowski]

Yes, in analog designs large W/L is nothing special. For example, the power fets in LDO could has W/L in the range of 18000/0.12. Input transistors in preamplifiers could also has large W/L for noise minimization, etc.

 

[ananthesh bhat]

Thanks a lot for the information Dominik.

 

[erikl]

I'm getting a W/L ratio for one transistor as 3500. Is this ok?

Absolutely ok, as Dominik explained above. But don't expect high analysis result accuracy, as such wide transistors usually aren't modelled very exactly.

 

[dick_freebird]

This is very normal especially in power drivers. You want
to finger the device appropriately to avoid crazy gate
resistance and possible current-flow debiasing (and the
tap rules will probably enforce this for you, though maybe
not so far as ensuring best performance - just latchup
free).