[SOLVED] Is this STD_LOGIC_VECTOR declaration allowed in VHDL

[TrickyDicky]

its for the convenience of the coder. when compiled, it is just 16 bits. But for fixed point logic, it provides a nice, easy way to separate the integer and fractional parts of the number. If it was 15 downto 0 you have to keep track of where the integer/fraction separations is.

 

[Jansi Meena]

Thanks Tricky