Would you let me know more about you said Synthesis?
I am confused that Synthesis's ouput have Netlist which is Ideal Clock STA(Synthe sis doesn't optimized clock delay), but what about delayed sim? What kinds of delay are simulated in here?
--> There is no need to simulate the netlist with delay here. You can confirm the function by formal verification. That is enough at after synthesis.
Please let
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Is this right? In briefly,
Presim : SDF(from PT) + Netlist(from DC)
Postsim : POST SDF(from SPEF) + POST Layout Netlist
There is no term like "PreSim" or "PostSim" in ASIC design flow.
Pre or Post is used to mention about the "state" of design.
Below can be a reference, you can put Pre or Post into each of them from Synthesis:
RTL - Synthesis - DFT insertion - Place - CTS - Route.
So, I dont understand what is your question regarding to Presim or Postsim. Sim is just an action on design flow, not a specific state.
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While back annotating, will we go to the synthesis stage? Can we use the sdf obtained from the PnR stage and give it as an input to the synthesis tool because this sdf/spef contains the actual delays due to RC also? Will such a resynthesis method give us a better optimized result?
There is a feature from Synopsys that allow you to use the Layout information from PnR as input for synthesis phase.
It reduce runtime, more optimization on congestion, timing ....
You can investigate it on Synopsys site. I dont know other EDA vendors have this feature or not.