Is this can be used as a floating forward biased diode ?

[leonken]

I found a floating varactor in cmos technology from Razavi's paper in 1999.
Is this floating varactor can be used as a floating forward biased diode in CMOS process without a latch-up problem?
Thank you!

 

[electronrancher]

The varactor is normally reverse biased, so this configuration is OK for a varactor. However for a forward-biasing diode, you'd need N+ buried layer to prevent significant vertical current. Since the substrate is p-type, it would be grounded. Forward biasing the pn junction you've shown above would create a vertical pnp. You would get conduction between the p&n, but you would also get a high-gain path between p & substrate. in a standard CMOS process this beta could be as high as 100 without n-buried layer, and could be as low as 10 with buried layer. So in either case it's not a very good device, as 10x your diode current would be shunted to ground.

What you need is a twin-well process, where you would use an N+ region inside the P+ region shown above. Now you can tie the N-well to the highest potential and the substrate remains grounded. For a device like an internal-charge pump for driving an NMOS LDO gate, the diode voltages will be higher than VIN so you can't tie to VIN. For this type of device, you must consider the biasing carefully for conditions of startup and shutdown.

 

[leonken]

The varactor is normally reverse biased, so this configuration is OK for a varactor. However for a forward-biasing diode, you'd need N+ buried layer to prevent significant vertical current. Since the substrate is p-type, it would be grounded. Forward biasing the pn junction you've shown above would create a vertical pnp. You would get conduction between the p&n, but you would also get a high-gain path between p & substrate. in a standard CMOS process this beta could be as high as 100 without n-buried layer, and could be as low as 10 with buried layer. So in either case it's not a very good device, as 10x your diode current would be shunted to ground.

What you need is a twin-well process, where you would use an N+ region inside the P+ region shown above. Now you can tie the N-well to the highest potential and the substrate remains grounded. For a device like an internal-charge pump for driving an NMOS LDO gate, the diode voltages will be higher than VIN so you can't tie to VIN. For this type of device, you must consider the biasing carefully for conditions of startup and shutdown.

Thank you very much.
I know what you mean.
Due to our n-well standard CMOS process, do you think it is possible to realize a floating diode?

I attached another figure. The n+ region is buried in a p+ region and all this two regions are buried in a n-well region.
The base terminal(n-well) of the vertical PNP transistor is floating.
my questions are
1. Does the standard CMOS process support this architecture?
2. If the emitter terminal of the vertical NPN transistor (N+, P+, n-well) is floating,
the diode can be relized or not?

 

[pillar_chen]

yes, I think it ok

 

[leonken]

yes, I think it ok

Thank you.

You think this diode can be realized by using a CMOS process.
And do you have the successful experience in making such a diode in a CMOS process?

 

[leonken]

The varactor is normally reverse biased, so this configuration is OK for a varactor. However for a forward-biasing diode, you'd need N+ buried layer to prevent significant vertical current. Since the substrate is p-type, it would be grounded. Forward biasing the pn junction you've shown above would create a vertical pnp. You would get conduction between the p&n, but you would also get a high-gain path between p & substrate. in a standard CMOS process this beta could be as high as 100 without n-buried layer, and could be as low as 10 with buried layer. So in either case it's not a very good device, as 10x your diode current would be shunted to ground.

What you need is a twin-well process, where you would use an N+ region inside the P+ region shown above. Now you can tie the N-well to the highest potential and the substrate remains grounded. For a device like an internal-charge pump for driving an NMOS LDO gate, the diode voltages will be higher than VIN so you can't tie to VIN. For this type of device, you must consider the biasing carefully for conditions of startup and shutdown.

You mean that the depth of N+ region and P+ region is different in the twin-well process? So, the N+ region can be buried in P+ region. Am I right?