Nov 25, 2014 #1 A anusha vasanta Member level 1 Joined Sep 23, 2014 Messages 34 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 251 Code: genvar n; generate begin Top_PipelinedCipher ROM1(clk,reset,data_valid_in,key_valid_in,key,mic_iv,valid_out,mic_iv_result); assign mic_h1_out= (mic_iv_result^mic_h1); Top_PipelinedCipher ROM2(clk,reset,data_valid_in,key_valid_in,key,mic_h1_out,valid_out,mic_h1_result); assign mic_h2_out=(mic_h1_result^mic_h2); Top_PipelinedCipher ROM3(clk,reset,data_valid_in,key_valid_in,key,mic_h2_out,valid_out,mic_h2_result); end endgenerate Last edited by a moderator: Nov 25, 2014
Code: genvar n; generate begin Top_PipelinedCipher ROM1(clk,reset,data_valid_in,key_valid_in,key,mic_iv,valid_out,mic_iv_result); assign mic_h1_out= (mic_iv_result^mic_h1); Top_PipelinedCipher ROM2(clk,reset,data_valid_in,key_valid_in,key,mic_h1_out,valid_out,mic_h1_result); assign mic_h2_out=(mic_h1_result^mic_h2); Top_PipelinedCipher ROM3(clk,reset,data_valid_in,key_valid_in,key,mic_h2_out,valid_out,mic_h2_result); end endgenerate
Nov 25, 2014 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,427 Helped 14,752 Reputation 29,786 Reaction score 14,105 Trophy points 1,393 Location Bochum, Germany Activity points 298,127 I don't understand the code. Why do you use generate at all, genvar isn't needed. It's just a list of regular module instantiations.
I don't understand the code. Why do you use generate at all, genvar isn't needed. It's just a list of regular module instantiations.
Nov 26, 2014 #3 A anusha vasanta Member level 1 Joined Sep 23, 2014 Messages 34 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 251 haa thankyou.without generate block we can do this right. i was just confused.
Nov 26, 2014 #4 A anusha vasanta Member level 1 Joined Sep 23, 2014 Messages 34 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 251 multiple iinstantiation problem in generate block i was using the output of one istantiation module in generate block taking that output as input of another module this is a multiple instantion issue is this possible with verilog. Code Verilog - [expand]1 2 3 4 5 6 7 8 9 10 Lgenvar m; generate for(m=BLOCKS;m<0;m=m-1) begin assign block_data[m]=data_new[(m*16)+15:(m*16)]; assign block_out[m]=(mic_h2_result^block_data[m]); Top_PipelinedCipher ROM4(clk,reset,data_valid_in,key_valid_in,key,block_out[m],valid_out,block_result[m]); assign mic_h2_result=block_result[m]; end endgenerate Last edited by a moderator: Nov 26, 2014
multiple iinstantiation problem in generate block i was using the output of one istantiation module in generate block taking that output as input of another module this is a multiple instantion issue is this possible with verilog. Code Verilog - [expand]1 2 3 4 5 6 7 8 9 10 Lgenvar m; generate for(m=BLOCKS;m<0;m=m-1) begin assign block_data[m]=data_new[(m*16)+15:(m*16)]; assign block_out[m]=(mic_h2_result^block_data[m]); Top_PipelinedCipher ROM4(clk,reset,data_valid_in,key_valid_in,key,block_out[m],valid_out,block_result[m]); assign mic_h2_result=block_result[m]; end endgenerate