Aug 18, 2007 #1 D dimshadow Newbie level 3 Joined Aug 25, 2006 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,293 When I use ncverilog to simulate large gate-level designs. ncelab usually took too much memory, more than 40G. Does anybody have a solution to this. Thanks very much.
When I use ncverilog to simulate large gate-level designs. ncelab usually took too much memory, more than 40G. Does anybody have a solution to this. Thanks very much.
Aug 18, 2007 #2 A aji_vlsi Advanced Member level 2 Joined Sep 10, 2004 Messages 643 Helped 85 Reputation 170 Reaction score 12 Trophy points 1,298 Location Bangalore, India Activity points 4,944 dimshadow said: When I use ncverilog to simulate large gate-level designs. ncelab usually took too much memory, more than 40G. Does anybody have a solution to this. Thanks very much. Click to expand... Can you show your exact command line? How large is your design in terms of gate count? 40GB sounds way too much. Do you have -access RWC? If so try removing that. Also use: -notimingchecks -nospecify Try using latest version/most stable version. Also try asking CDN directly. Regards Ajeetha, CVC www.noveldv.com
dimshadow said: When I use ncverilog to simulate large gate-level designs. ncelab usually took too much memory, more than 40G. Does anybody have a solution to this. Thanks very much. Click to expand... Can you show your exact command line? How large is your design in terms of gate count? 40GB sounds way too much. Do you have -access RWC? If so try removing that. Also use: -notimingchecks -nospecify Try using latest version/most stable version. Also try asking CDN directly. Regards Ajeetha, CVC www.noveldv.com