Is there any way to reduce memory used by ncelab?

[dimshadow]

When I use ncverilog to simulate large gate-level designs. ncelab usually took too much memory, more than 40G.

Does anybody have a solution to this.

Thanks very much.

 

[aji_vlsi]

When I use ncverilog to simulate large gate-level designs. ncelab usually took too much memory, more than 40G.

Does anybody have a solution to this.

Thanks very much.

Can you show your exact command line? How large is your design in terms of gate count? 40GB sounds way too much. Do you have -access RWC? If so try removing that. Also use:

-notimingchecks
-nospecify

Try using latest version/most stable version.

Also try asking CDN directly.

Regards
Ajeetha, CVC
www.noveldv.com