If you are using Xilinx FPGAs, then all the flip-flops and RAM are automatically initialized to zero during configuration. Or you can initialize them to specific states in your HDL, such as the Verilog register declaration "reg foo=1;".
If you are using Xilinx FPGAs, then all the flip-flops and RAM are automatically initialized to zero during configuration. Or you can initialize them to specific
Is there have some materials denote that xilinx FPGA will be automatically initialized to zero when power on .
whether FPGA's flip-flops will be a random state when power on .
If it will be intialized to zero why we need to connect a external rest signal to FPGA !
and if that's true whether this program can implement rest function(like external rest signal ) when power on
module rst(clock,rst);
input clock;
output rst;
reg [2:0] rst_cnt;
reg rst;
always@(posedge clock)
begin
if(rst_cnt!=3'd7) rst_cnt<=rst_cnt+3'd1;
end
always@(posedge clock)
begin
if(rst_cnt!=3'd7) rst<=1'b0;
else rst<=1'b1;
end
Matrix_YL, you didn't say what type FPGA you have, so I can't point you to the proper data sheet.
I *never* use a reset input in my FPGA projects. The configuration download is sufficient to preset all states. I design my FPGA logic so it automatically recovers from unexpected states (cosmic ray hits or whatever).
Ok, I see you want to generate a low-true reset pulse for some other purpose. You still need to initialize those registers, or else the Verilog simulator will use X. Here's my Verilog coding style:
If you press the "Code" button instead of "Quote", it will preserve your source code indenting.
jay_ec_engg, if you really need a logic reset input, simply use a regular I/O pin. FPGAs don't have a dedicated reset pin. Well, Xilinx FPGAs don't. Pull-up issues depend on your FPGA type. Refer to its data sheet.
Which Xilinx FPGA? They make many different types.
With Spartan-3 and Virtex families, the software tools generate a configuration bitstream that initializes registers and block RAMs to zero unless your design specifies different values. Beware that HDL simulators will default registers to X if you don't specify an initial value.
Yes, I never connect an external reset input to my FPGA logic. Of course, I do connect the configuration signals - everyone needs them.