Is there any problem in a design with a lot of wires?

[win3y]

Hi Everybody;

I am going to fabricate my design using DC, Prime Time and Astro.
But I am wondering there is any problem in the design with a lot of wires while implementing Back-End work? Is there anyone had experience with this?
My design has 3 modules connected each other by some wires [1023:0]
If any please suggest me some solutions.

Thank you very much!

Win3Y

 

[denmos]

Hi Everybody;

I am going to fabricate my design using DC, Prime Time and Astro.
But I am wondering there is any problem in the design with a lot of wires while implementing Back-End work? Is there anyone had experience with this?
My design has 3 modules connected each other by some wires [1023:0]
If any please suggest me some solutions.

Thank you very much!

Win3Y

Please take care of your planning of pin connections:
- The block pins alignment will reduce the total wire-length and DRC also.
- The channel between sub-blocks should to be plan enough for both pin-to-pin connection and other power connection.
- Clock pins should be place in center of stdcell area. that will control your skew better.
- To get better slack, the in/out pins should be given of a buffer and prune the number of buffer also.

, Denmos: vinh.camau@gmail.com

 

[win3y]

Please take care of your planning of pin connections:
- The block pins alignment will reduce the total wire-length and DRC also.
- The channel between sub-blocks should to be plan enough for both pin-to-pin connection and other power connection.
- Clock pins should be place in center of stdcell area. that will control your skew better.
- To get better slack, the in/out pins should be given of a buffer and prune the number of buffer also.

, Denmos: vinh.camau(at)gmail.com

Thank you for your suggestion.

But I am still wondering whether my design has problem in such a big wire.
Does It cause error? And even not working correctly?

Win3Y

 

[Nir Dahan]

If you got a lot of wires criss crossing the chip it might cause congestion problem (not enough space for a lot of wires that need to go through a specific area).
Be especially careful near SRAM blocks since a lot of times routing above them is not allowed and they create a "hole" in the floor plan.

when doing the floor planning try to think carefully where to put blocks like SRAMs and other hard macros.

here are two posts that might be helpful for you:
https://asicdigitaldesign.wordpress.com/2007/07/01/some-layout-considerations/
https://asicdigitaldesign.wordpress...er-buses-more-tricks-for-switching-reduction/

the second post is considering more low power aspects but should be interesting enough.

good luck,

ND
https://asicdigitaldesign.wordpress.com

 

[ljxpjpjljx]

also if you use many wires in your design , the backend guy will be crazy!

 

[win3y]

If you got a lot of wires criss crossing the chip it might cause congestion problem (not enough space for a lot of wires that need to go through a specific area).
Be especially careful near SRAM blocks since a lot of times routing above them is not allowed and they create a "hole" in the floor plan.

when doing the floor planning try to think carefully where to put blocks like SRAMs and other hard macros.

here are two posts that might be helpful for you:
https://asicdigitaldesign.wordpress.com/2007/07/01/some-layout-considerations/
https://asicdigitaldesign.wordpress...er-buses-more-tricks-for-switching-reduction/

the second post is considering more low power aspects but should be interesting enough.

good luck,

ND
https://asicdigitaldesign.wordpress.com

Some given posts are really interesting. Thank you very much.
To ljxp..: You are absolutely right ! I am that Back-End guy

Is there anyone here who did successfully with [1023:0] bus wide ?

W3Y