Re: How to increase fanout of CMOS buffer
CMOS IO standard has no fixed fan-out limit. Everything depends on required speed. You should also consider wiring/PCB capacitance, it is possibly higher than logic input capacitance. I also presume that "100's" of paralleled interfaces involve a considerable wire length and you need to think about distributed buffers.
Your suggested solutions are just useless or even making signal quality worse. If necessary use multiple cascaded bus buffers, e.g. HC541.