is there a LVTTL port in Virtex II Pro?

[OvErFlO]

lvcmos33 +virtex ii pro

Does it exist LVTTL port in Virtex II Pro ?


Thanks

 

[davorin]

Re: LVTTL in virtex II Pro

First search result in google:


hxxp://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=14965

 

[speedoak]

Re: LVTTL in virtex II Pro

V2P has some limitation when talking to LVTLL(3.3V IO), xilinx has a apps talking about this issue. if you donot design the board correctly, you will damage the chip. please visit the following link
https://www.xilinx.com/bvdocs/appnotes/xapp653.pdf

 

[AMCC]

Re: LVTTL in virtex II Pro

I,
I'm using Virtex II - Pro, (V2p7) with more than 200 I/O configured as LVDCI3.3 (wich is similar to LVTTL). I had no problem until now...
If you have a correct supply and terminators (in case of LVDCI) I think you will have NO problem.
Note that https://www.xilinx.com/bvdocs/appnotes/xapp653.pdf is for PCI compliance (and you should read-it carefully if you are using your FPGA for direct PCI interface).

AMCC

 

[Git]

Re: LVTTL in virtex II Pro

In the Spartan3 the dedicated configuration pins run at VCCAUX which has to be at 2.5V, while the dual purpose configuration pins on bank 4 and bank5 will run at VCCO for those two banks which will be 3.3V if you want all LVCMOS33 outputs or similar.

Is the Virtex similar, and if so would you share how you got over the problem?. Xilinx mention it but are not very specific.

Git

 

[AMCC]

Re: LVTTL in virtex II Pro

Hi,

In my design ALL VccAux are 2,5V and ALL VCCO are 3.3V.


"Before and during configuration, all configuration I/O pins are set for the
LVCMOS25(12mA, fast slew rate) standard when VCCO is 2.5V. It becomes LVCMOS33
(16mA, fast slew rate) when VCCO is 3.3V." (VirtexII-Pro Platform User Guide - UG012 pag.286) (See also page 287 that has a table concerning this matter).

You can also take a look to page 288 where a "Mixed Voltage Environments" operation is explained.

Hope this helps.

AMCC