Is there a counter with carry in Matlab simulink ?

[agana56]

matlab question

Hi all
Is there a counter with carry in matlab simulink (i mean that when there is over flow a carry is out )

I want to know after using the block ( signal to workspace ) how to take the stream of bits from the matlab command window in a text file and use it as an input signal to another system made in Quartus II (it is a software of Altera it is like FPGA advantage )
I mean that if i succeed to get this text file which has the stream of bit like this
t=[ 1 0 1 0 0 0 1 ............... 0 1 ]
i want at every clk one bit only is an input to the system ( note that the lengh of this vector is not known )
i tried to make a testbench but it is not right
thx for help


[/b]

 

[ahmad_abdulghany]

Re: matlab question

I'm not sure that i fully understood your problem, but i think you are asking about some sort of counter blocks in Simulink, Am I right?
I think that may be helpful: **broken link removed**

Do let me know if you need something else,
Best Regards,
Ahmad,

 

[agana56]

Re: matlab question

hi all

I need to know two thing seperated

1) Is there a counter with carry in matlab simulink (i mean that when there is over flow a carry is out )

2) i have a variable t=( 0 1 0 0 0 1 1 1 ......... 0 1) its length for examble is (2220 ) when i display it in command window it doesn't appear complete , example when i type in the command window >> t' then i press enter this will appear
Columns 2173 through 2184

0 0 1 1 0 0 1 1 0 0 0 0

Columns 2185 through 2196

1 1 1 1 1 1 0 0 0 0 0 0

Columns 2197 through 2208

1 1 0 0 1 1 0 0 1 1 0 0

Columns 2209 through 2220

1 1 1 1 1 1 0 0 0 0 0 0

it dosen't start from the begining
what can i do ?

3) if i have a vector t =( 0 1 0 0 0 1 1 1 ......... 0 1) in a txt file how can i make it as an input signal to a system made in quartus II (it is a software of altera it is like FPGA advantage ) but one bit each clk , is it don by testbench or what ?

thx for help

 

[ahmad_abdulghany]

Re: matlab question

1) Is there a counter with carry in matlab simulink (i mean that when there is over flow a carry is out )

**broken link removed**

in the above figure, this block is discussed in the link i provided before, you can refer again to it.. anyway, If you are seeking to get carry in order to cascade some counters and the next one is to be reset at carry overflow or something like that, then you can use the optional output 'Hit' as a carry, this can be done at not only on overflow condition, but also at any value you want by assigning that value in counter dialog box in the 'Hit value' field.. and the input 'Rst' can be used as the reset input to your counter block..

2) i have a variable t=(0 1 0 0 0 1 1 1 ......... 0 1) its length for examble is (2220) when i display it in command window it doesn't appear complete , example when i type in the command window >> t , then i press enter this will appear
Columns 2173 through 2184

0 0 1 1 0 0 1 1 0 0 0 0

Columns 2185 through 2196

1 1 1 1 1 1 0 0 0 0 0 0

Columns 2197 through 2208

1 1 0 0 1 1 0 0 1 1 0 0

Columns 2209 through 2220

1 1 1 1 1 1 0 0 0 0 0 0

it dosen't start from the begining
what can i do ?

You mean that this is a vector? I am using Matlab 7, and to do a test for your problem, I wrote:

>>a=ones(2222);

then

>>disp(a);

or

 >> a

displayed the complete vectore, I don't know in fact what is the reson of yours..

3) if i have a vector t =( 0 1 0 0 0 1 1 1 ......... 0 1) in a txt file how can i make it as an input signal to a system made in qu(at)rtus II (it is a software of @ltera it is like FPGA advantage ) but one bit each clk , is it don by testbench or what ?

Does qu(at)rtus mean Qu'a'rts ?? and @ltera mean 'A'ltera (w/o cotations) ?? I think so, I think you can make it using a Matlab generated test bench, if you have the variable 't' in a vector, then you can write a very simple code to loop on that vector element by element, and if the current element is '1' then it prints the code corresponding to forcing the signa to one in VHDL code after certain period increased as loop counter increas, and vice versa for the case of '0' element.

I hope that be helpful anyhow !

Kind Regards;
Ahmad,

 

[agana56]

Re: matlab question

Does qu(at)rtus mean Qu'a'rts ?? and @ltera mean 'A'ltera (w/o cotations) ?? I think so, I think you can make it using a Matlab generated test bench, if you have the variable 't' in a vector, then you can write a very simple code to loop on that vector element by element, and if the current element is '1' then it prints the code corresponding to forcing the signa to one in VHDL code after certain period increased as loop counter increas, and vice versa for the case of '0' element


yes you are right .
how can i make this code?

thx for help

 

[ahmad_abdulghany]

Re: matlab question

This is a sample code, you will have to re-edit it to comply your problem, but it gives only the idea..
Note: I didn't test or run it, so you have to debug it yourself..

function y=tb(a)
fid=fopen('VHDL_signal_assignment.vhd','w');
fprintf(fid,'\n---Write your entity here---');
fprintf(fid,'\n---Write your archetecture begininning here---');

[b]%correction:[/b]
a=a'; % this line should be added

for i=0:(size(a)-1)
    T=2; % as an example of period assignment of 2ns
    if a(i+1)== 0 % then the signal 's' is to be forced with value '0'
        fprintf(fid,'s<=''0'' after %d ns\n',i*T);
    continue;
    end
    if a(i+1)==1 % then the signal 's' is to be forced with value '1'
        fprintf(fid,'s<=''1'' after %d ns\n',i*T);
        continue;
    end
end
fprintf(fid,'\n---end your arctecture here---');
fclose(fid)

Best Regards,
Ahmad,