Sep 18, 2008 #1 Mkanimozhi Full Member level 4 Joined Aug 8, 2007 Messages 193 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,296 Activity points 3,445 Hi, I need to change the wire state form logic o to logic 1 when some transaction on the input vector value ,like in vhdl we have attributes say 'event ,'high and 'low like tat is there any attribute is there in verilog. Regards Kanimozhi.M
Hi, I need to change the wire state form logic o to logic 1 when some transaction on the input vector value ,like in vhdl we have attributes say 'event ,'high and 'low like tat is there any attribute is there in verilog. Regards Kanimozhi.M
Sep 22, 2008 #2 K kvingle Full Member level 5 Joined Nov 5, 2007 Messages 244 Helped 33 Reputation 66 Reaction score 12 Trophy points 1,298 Location India. Activity points 2,574 Yes. There is always@(posedge clock ) construct to play with.