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Is their any attribute is there in verilog

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Mkanimozhi

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Hi,
I need to change the wire state form logic o to logic 1 when some transaction on the input vector value ,like in vhdl we have attributes say 'event ,'high and 'low like tat is there any attribute is there in verilog.

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Kanimozhi.M
 

kvingle

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Yes. There is always@(posedge clock ) construct to play with.
 

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