Is their any attribute is there in verilog

[Mkanimozhi]

Hi,
I need to change the wire state form logic o to logic 1 when some transaction on the input vector value ,like in vhdl we have attributes say 'event ,'high and 'low like tat is there any attribute is there in verilog.

Regards
Kanimozhi.M

 

[kvingle]

Yes. There is always@(posedge clock ) construct to play with.