In a synthesis-based design flow, first-order timing errors
(internal and fanout loading delays) are fixed during the
optimize-against-constraints cycle.
Post-C-extracted timing simulations can't really be done
well until the entire layout is "done". So a C-only timing
verification will show post-synthesis faults potentially.
RC extraction takes longer to run the more complex netlist
and will show errors (again, potentially) that C-only and
wireload models did not (wireload using only a L based
estimate, perhaps per-layer-segment, lumped but still
unaware of neighbor nets, coupling and branching (R).
Onion, layers, cry, repeat.