okguy said:You have a design problem. The ratio between M5 and M12 should be an interger number : 7 or 8, not 7.5!
No way to draw a good layout. I suggest you to increase a little your ref resistor to keep the same current in your diff pair and go for a ratio of 8.
Then, your layout becomes : M12,M12,M12,M12,M5,M12,M12,M12,M12 :idea:
duron999 said:okguy said:You have a design problem. The ratio between M5 and M12 should be an interger number : 7 or 8, not 7.5!
No way to draw a good layout. I suggest you to increase a little your ref resistor to keep the same current in your diff pair and go for a ratio of 8.
Then, your layout becomes : M12,M12,M12,M12,M5,M12,M12,M12,M12 :idea:
Hello, i don't understand what mean "the ratio in interger number:7 or 8, not 7.5!"
and below is the overall circuit, which transistor need to do matching ???
How to see which transistor need to match ??? any rules ???
If PMOS can not match with NMOS, any method to match them?
Can i change the W/L ratio for matching so that the size can match?
For example: orginial is 18u/0.8u = 22.5, can i change to 4.5u/0.2u ?
rfsystem said:Sorry the jpg vanish!
I rember there was indeed an active load.
Added after 6 minutes:
The jpg load time was more than 120s
The 40kOhm resistor is for biasing the current. You can use instead a circuit similar to a PTAT but with a NMOS (PMOS) biased at two NMOS (PMOS) diode voltages used as resistor. The NMOS as resistor is then operating in linear mode. So there is a MOS only circuit. The termperature behaviour is not ~T but for 50% current biasing it is ok.
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