Is the common centroid method obsolete ?

[Han]

Common centroid

Hi All,

I know that common centroid method has been used for quite long time in order to improve matching.
I never used common centroid or interdigitate methods for matching. I use large area devices and place matching devices close to each other, and I never had mismatch problems. One of my colleague claims that for deep submicron process the common centroid method is obsolete and anyway not sutible for high speed circuits.
Please share with me your thoughts...

 

[steer]

Re: Common centroid

Generally, I agree with your collegue. In most practical cases he's right.

 

[duron999]

Re: Common centroid

oh ~ i have a problem is:
If i have a PMOS1 and the ratio(W/L) is 66u/0.8u ,
NMOS2 14u/0.8u, PMOS2 2.4u/0.8u,

the size of PMOS is very very large compare with PMOS2,
can i use Common centroid method the match the size ???
thanks !

 

[Colbhaidh]

Re: Common centroid

Just using multiple pmos transistors of unit size should be sufficient for matching.
eg 28 transistors each of 2.4/0.8um connected to give 67.2/0.8um.
If you can fit all these in say an area of 100x100um matching should be pretty good.

 

[Han]

Re: Common centroid

I agree with Colbhaidh.However, the small device 2.4/0.8um may suffer from Vt mismatch due to it's small area (roughly 10mV, depending on your process). If this is current mirror, you might want to use larger devices.

 

[cetc1525]

Common centroid

is o.8um is your most small size?I think the well matched transistors' length will be3 times than the feature size.
I think centroid is useful.

 

[jiangwp]

Re: Common centroid

First , the common centroid is not used everywhere.
when the symmetry and high match is need for themal, noise and offset etc. consideration, the common centroid is used.
May be the dummy is also a good way for improving the match.

 

[duron999]

Re: Common centroid

Please see below picture, M1 & M2 is very large(66u/0.8u) and
M8 (2.4u/0.8u) & M12 (1.2u/2.4u) is much smaller,
When we do the layout, do we use the Common centroid Method
so that M1 & M2 divide into a few part to match M8 & M12 ???

 

[okguy]

Re: Common centroid

You have a design problem. The ratio between M5 and M12 should be an interger number : 7 or 8, not 7.5!
No way to draw a good layout. I suggest you to increase a little your ref resistor to keep the same current in your diff pair and go for a ratio of 8.
Then, your layout becomes : M12,M12,M12,M12,M5,M12,M12,M12,M12 :idea:

 

[j2005]

Re: Common centroid

In case you are confused, I think okguy was referring to M5 and M8. But I agree with his method. Anyway, there is no point trying to match M1, M2, M8 & M12 together. M12 is NMOS, you can't match NMOS with the other PMOSs. Better to just match M1 & M2. And then match M5 & M8.

 

[lhenfalculan]

Re: Common centroid

I agree that M1 and M2 should be match and its ok not to match it with M5 and M8.

 

[duron999]

Re: Common centroid

You have a design problem. The ratio between M5 and M12 should be an interger number : 7 or 8, not 7.5!
No way to draw a good layout. I suggest you to increase a little your ref resistor to keep the same current in your diff pair and go for a ratio of 8.
Then, your layout becomes : M12,M12,M12,M12,M5,M12,M12,M12,M12 :idea:

Hello, i don't understand what mean "the ratio in interger number:7 or 8, not 7.5!"

and below is the overall circuit, which transistor need to do matching ???
How to see which transistor need to match ??? any rules ???

If PMOS can not match with NMOS, any method to match them?
Can i change the W/L ratio for matching so that the size can match?
For example: orginial is 18u/0.8u = 22.5, can i change to 4.5u/0.2u ?

 

[cretu]

Re: Common centroid

There is no way you can match PMOS and NMOS transistors. What you have in your design is basicly an amplyfier with some pmos current mirrors. Match the 2 transistors in the diff pair and the pmoses for the current mirror. The same for the 2 nmoses that you use as a load.

So concentrate on those things. And for M1 and M2 I used in several IC's the commone centroid technique and it gave the best results. If you are worried about the offset maybe you can try a second order common centroid which should reduce the overall offset

You have a design problem. The ratio between M5 and M12 should be an interger number : 7 or 8, not 7.5!
No way to draw a good layout. I suggest you to increase a little your ref resistor to keep the same current in your diff pair and go for a ratio of 8.
Then, your layout becomes : M12,M12,M12,M12,M5,M12,M12,M12,M12 :idea:

Hello, i don't understand what mean "the ratio in interger number:7 or 8, not 7.5!"

and below is the overall circuit, which transistor need to do matching ???
How to see which transistor need to match ??? any rules ???

If PMOS can not match with NMOS, any method to match them?
Can i change the W/L ratio for matching so that the size can match?
For example: orginial is 18u/0.8u = 22.5, can i change to 4.5u/0.2u ?

Added after 4 minutes:

To be more specific:

1. Match M1 with M2 (common centroid) differential pair
2. Match M3 with M4 - it's not an absolute must but it helps a lot
3. Match the PMOS current mirror - M8 with M5 and M7(only if you need a certain relationship between the currents supplied by this 3 transistors)

I hope this helps

 

[terryssw]

Re: Common centroid

What parameters of the opamp will be affected by the mismatches effects? I think offset is one parameters, but anything else? (I don't think DC gain and GBW will be affected seriously by mismatch.)

 

[JPR]

Re: Common centroid

Several things:

For matching , in order of importance:
M1 to M2 - critical
M3 to M4 - critical
M5 to M7 (with 3:1 ratio) - somewhat
M3,4 to M6 (with 6:1 ratio) - somewhat

The 1st stage gain will reduce the need for matching to M6 and M7, so it may not be important to you. With such short lengths on the input stage, however, I would guess that the 1st stage gain is not all that high, so 2nd stage matching might become important.

If the 2nd stage matching is important, you have a design flaw - a built in offset from the 1st stage to the 2nd stage. The current density in M6 should match the current densities in M3 and M4. Since the current in M6 is 6x higher than the current in either M3 or M4, you would want the ratio of M6 to M3 or M4 to be 6:1 (which would be 84u/0.8u, instead of 64u)

I would also use a unit sized device, with multiple devices in parallel, rather than adjusting the width.

If matching is critical, the lengths on your devices should be evaluated, as the delta-L will probably dominate your matching with only 0.8u wide devices (unless this is on a 0.2u or smaller geometry foundry) (I would think that you should extend the length on M1, M2, M3, M4, M5, M6 and M7.

 

[sergeyr77]

Re: Common centroid

No need matching for M8-M5-57, common centroid for M1-M2 must, for M3-M4 is very useful - all to reduce offset, especialy for big transistors where gradient across die may be large.
But I think you have a big problem. All transistors have substrait-source shorted.
May be it is justified for M1, M2 to use separate N-well, but for 5 stacked transistors and transistor for zero compensation it is not true if you don't use some exotic proccess.

 

[rfsystem]

Re: Common centroid

As point out M1/M2 and M3/M4 are equal important and belong to the same class. The ratio M5/M7 should be corrected so that the mirror drain voltages are matched. The area of M3/M4 is smaller and therefore I think matching dominated by M3/M4. It could be increased by increasing the area by constant W/L. So the matching to the output device is not violated. Interdigitized stripes are the common solution today. More important is that the NWELL edges are 2-3 times the DRC so that the implant is not affected. The metal connection pattern should not overlap the hole matched area. Instead a plate shield or only a fill pattern matched to the stripes should be used. Or a fill keep out area.

 

[duron999]

Re: Common centroid

i have another question is how to change the 40Kohm to active load?
use PMOS or NMOS and how to find the W/L ratio ? thanks !

 

[rfsystem]

Re: Common centroid

Sorry the jpg vanish!

I rember there was indeed an active load.

Added after 6 minutes:

The jpg load time was more than 120s

The 40kOhm resistor is for biasing the current. You can use instead a circuit similar to a PTAT but with a NMOS (PMOS) biased at two NMOS (PMOS) diode voltages used as resistor. The NMOS as resistor is then operating in linear mode. So there is a MOS only circuit. The termperature behaviour is not ~T but for 50% current biasing it is ok.

 

[duron999]

Re: Common centroid

Sorry the jpg vanish!

I rember there was indeed an active load.

Added after 6 minutes:

The jpg load time was more than 120s

The 40kOhm resistor is for biasing the current. You can use instead a circuit similar to a PTAT but with a NMOS (PMOS) biased at two NMOS (PMOS) diode voltages used as resistor. The NMOS as resistor is then operating in linear mode. So there is a MOS only circuit. The termperature behaviour is not ~T but for 50% current biasing it is ok.

i repost it, thanks !