is safe to create a clock to control an A/D using FPGA?

[jonatan]

I have a DIGILENT D2S board with Spartan2E- (XC2S200E) with 50MHz clock in the board and one A/D converter ADS2807 from Texas. The A/D works with the clock range from 100Khz up to 50MHz, and do the conversion in continuous acquisition mode.

I would like to know if is safe to create a clock with 25MHz from FPGA board througth clock divider (50MHz/2) to serve as input clock to A/D using LVTTL I/O drive configuration in FPGA Pin out?

How do the FPGA behavior about temperature in this case? Is there a limit to this temperature, of course, can someone explain something about that?

Do I need to verify this case in "Analyse Power (XPower)" option in ISE.

Thanks in advance...

 

[tlp71@hotmail.com]

i think yes, you can safely create a 25Mhz, if you would have a clear clock you can use the 50Mhz clock to gate the 25Mhz and no have glitch.
for the temperature if your device is commercial you can have the temp limit at 85 °C if yor device is in industrial ranhe you can takle the 100 °C.
Bye.
G.

 

[sanjay]

Yes I think it is perfectly safe. WE tried driving a clock from Virtex -11 running on 40MHz to and ADC of 40MHz. I think the only difference that u might want to consider is the impedance factor into account... the rest everything should be just fine..

 

[skynet]

Yes, it is safe to drive a A/D Converter from an Xilinx FPGA, but I do suggest that you use the DCM from Coregen built-in DPLL device, it able to generate a 25MHz from 50Mhz by dividing 50Mhz. By using this DCM, you also unable to connect to A/D from a clock output pin from FPGA. So you save routing resource in your FPGA. Hope this help..!

 

[flatulent]

The only thing to make sure of is the jitter, if any, from the generation of the clock. You should examine the clock output on a spectrum analyzer and look for phase noise sidebands. This jitter, if any, may not be of any significance in your design or it may be very critical.

 

[yev15]

The jitter is very serious problem in the flash ADC. Once, when i tried to create a 40MHz clock using Acex FPGA, the jitter caused a high noise in the ADC.

 

[kilone]

YES, Jitter!!! That is really the problem!
The jitter of the clock generated by DCM output can be 40~80 ps, and even worse (>100 ps) when more than one stage DCM were adopted. High performance ADCs, however, will only tolerate jitters less than 10 ps for critical applications. Therefore, spectrum of sampled signals may be fairly deteriorated when excessive clock jitter provided.

 

[brmadhukar]

Hi,
I have designed a product that works with a ADC sampled from a clock generated using an FPGA. The sample clock varies from 2MHz to 20MHz. The source for this is a 90MHz clock derived from the RF using a 20MHz TCXO.

Observations: When the sample clock to adc is generated using a divider (not an NCO) the performance is good otherwise it comparitivel bad. So AVOID NCO to generate sample clock.

BRM

 

[speedoak]

I donot think you will have any problem. it is pretty safe