Is putting after clause a gd practise to simulate to verify

[s3034585]

Hi Guys
I have been simulating my vhdl code in model sim but when i synthesis it and put on hardware some times the code dosnt behave as seen the simulations. I mean that, after synthesis delay comes into picture but while simulating in modelsim there is not delay hence the simulation looks right.

So in order to see the simulation similar to real time is it fine to add some delay for every signal assignment and then simulate in modelsim.

I am pretty confused can any one pls let me know about it.

Wht is a good practise to simulate the code so that when it goes on hardware it will work exactly as we wanted.

Thanks in advance

 

[yasser_shoukry]

Re: Is putting after clause a gd practise to simulate to ver

Hi Guys
Wht is a good practise to simulate the code so that when it goes on hardware it will work exactly as we wanted.

Make sure that there is no "Infered Latches" in your design , to know that you have to read all warnings of the "Synthesis Report". If a Latch is infered , this means that you have broken one of the Combinational Circuit rules.

For the first question, If you are using ISE (xilinx tool) there is a post-synthesis simulation which will show you really how the hardware will behave after synthesisng your code.

Yasser.