Ids rises approx. exponentially with Vgs between Vgs=0 and Vth, so if you know two Ids values in this range, you can draw a curve. But this only makes sense for a single device. And think of Ids' temperature dependency!Question #1: Is there an equation or rule of thumb that allows me to put a bound on Ids for 0<Vgs<Vth ? i.e. sub-threshold Ids (For example: Ids<1uA)
Also graphs of leakage current versus temperature indicate leakage currents which are orders of magnitude smaller than the worst case listed in the spec table.
Question #2: Is the real leakage current the 1uA max in the spec table or the 20nA in the graph?
Such graphs usually show typical values, whereas specs give max. values (hopefully at a specified max. temperature), which perhaps are tested for non-exceedance - if you are lucky.
You never could risk this for volume production. In the latter case you should have an auxiliary (higher) voltage which allows you to apply Vgs=0 or even Vgs > 0 (PMOS).
Why can't you put Vgs to 0V?
Post your circuit diagram.
If you use a CMOS circuit to drive the MOSFET gate then you can drive the Vgs to between 0V and the supply voltage with no power dissipated, other than the leakage current of the CMOS circuit and the MOSFET.
You can't really do better than that.
I have found several references that state that Ids drops by a factor of 10x for every n*60mV drop in Vgs; where "n" is a characteristic of the FET device (1 < n < ?).
n= 1+ Cb/Cg; where Cb is bulk capacitance, Cg is gate capacitance.
https://en.wikipedia.org/wiki/Subthreshold_slope
This is exactly the kind of "rule" I was looking for. If I only knew what the range of "n" was for real devices.
Equations can be found in analog design text books. But I don't believe that it makes sense to refer to equations in this case, equations can only represent the typical values, the behavior of an average transistor. A design must consider type variations. You better refer to min/max values in datasheets.
Here's the right value for the subthreshold factor n from Binkley's book: View attachment 122181
So for a single device you could get along with the a.m. method (max. temperature considered!), but think of a possible necessity for replacement!
Thanks that is just the kind of authoritative source I was looking for. Unfortunately the highlighted section in the link only gives an example value for "n". What is needed is a maximum practical value for "n". At the bottom of the linked page the author mentions a minimum value for "n"; does he continue on the next page to discuss a maximum?
This is quite possible. May be it's set so high that they just have to run random sampling tests.I also suspect that typical max leakage specs may be overly pessimistic (it's suspicious that it is so often 1uA) - any insight about that?
Or is it as I suspect that the Vgs=0 leakage spec is just an arbitrarily chosen "good enough" spec for production test?
At MOS transistors the always existent bulk-to-drain reverse-biased junction diode usually has maximal the same leakage current as the transistor @ Vgs=0 - rather less - it depends on Vds and on temperature, too, of course. Should also be specified, anyway. Ids measurements always include this current.For example using my specific device Vth (Vgs=-0.45 @ Ids=250uA) the max Ids @ Vgs=0 found using the subthreshold slope method would be: 0.45V/0.1V = 4.5; Ids < 250uA / 10^4.5 = 8nA
So does some non-channel path or effect dominate at Vgs=0 making the max leakage two orders of magnitude higher than predicted by the slope method?
For volume production you should always respect the border values, as FvM pointed out above - otherwise you dismiss the manufacturer of their responsibility.I understand that many people would just say accept what the datasheet says and design around it; but, when pushing on the cost/performance limit I feel the need to really understand what's happening in the gaps. And numerous times I have found errors and inconsistencies in the datasheets.
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