is latch with registered enable is equivalent to flipflop?

[manojkhandelwal]

Hi all,
I just want to know whether the two circuits are equivalent (1 and 2). By equivalent i mean exactly same timing characteristics

1. A latch with its enable signal (en) and input "in". But, this enable signal is the output of a flip flop (clock signal of this flop is "clk").

2. A flipflop with clock signal "clk" and input(in) is ANDed with enable (en).

Note: the latch output equals input when en=1

Thanks in advance,
manoj

 

[TrickyDicky]

no, because the latch is not clocked, and when enable is high, it will have minimal delay.

general rule for fpgas - dont use latches.

 

[manojkhandelwal]

Hi tricky,

Iam sorry, but i didnt get what your saying..
Can u please elaborate a little bit more..

Thanks,
Manoj

 

[TrickyDicky]

the latch is transparent when enable is asserted. so any glitches are also passed through
you wont get glitches with the FF.

 

[manojkhandelwal]

ok,
i heard from a lot of people that dont use latches in fpga's.......then why there are dedicated latches present (like registers) in some fpga devices.......?
Anyways, i was just asking because my RTL contained a latch and a register was inferred by the tool........strange right?

 

[TrickyDicky]

there are very few (if any) latches in fpga, they are all d type flip flops.
can you post somwe code>?
why do you want a latch?