First thanks for your reply.
I try to make my question clearly.
My module has two interfaces: one is asynchronous and the other is synchronous with gated-clock.
I use a register need to be set by asynchrounous side and cleared by synchronous side.
I have to use the write and other control signals to generate a clock to set the DFF value. Then I will have a generated clock and another clock from synchronous to the DFF.
I know this will cause troubles on STA, but if I use asynchronous method to clear the DFF, the DFT will become diffuclt.
I am not good at this. Hope to get more information or solution from you.
Thanks in advance.
Best regards.