Is it there any disadvantage of two clock to one DFF?

[cnspy]

In my design, there are two clocks though a MUX to a DFF clock.

Does this kind of design have any disadvantages?

thanks in advance.

 

[cawan]

For what purpose? You need switching time from one clock to another clock through the multiplexer. Anyway, try to control your phase noise on both of your clock.

 

[wadaye]

In my design, there are two clocks though a MUX to a DFF clock.

Does this kind of design have any disadvantages?

thanks in advance.

Hi cnspy:

Is the clock will switch when the CHIP working? On the fly and not have

different design consideration.

wang1

 

[masai_mara]

It will be a problem if you dont take care of the switching between the two. It also depends on how the inputs are given to the DFF in each of the clock modes.

 

[cnspy]

First thanks for your reply.

I try to make my question clearly.

My module has two interfaces: one is asynchronous and the other is synchronous with gated-clock.
I use a register need to be set by asynchrounous side and cleared by synchronous side.
I have to use the write and other control signals to generate a clock to set the DFF value. Then I will have a generated clock and another clock from synchronous to the DFF.
I know this will cause troubles on STA, but if I use asynchronous method to clear the DFF, the DFT will become diffuclt.
I am not good at this. Hope to get more information or solution from you.


Thanks in advance.

Best regards.