biju4u90
Full Member level 3

Is it possible to assign some value to a port or signal from VHDL code and test bench simultaneously. For example, I have a port named 'sda'. For some conditions, I need to drive this 'sda' from the code. At some simulation time, I need to make sda = '0' from test bench. Is it possible to do this?? I tried by defining sda as inout port. But since the value assigned to sda in code and value assigned in test bench drives the port simultaneously, my sda value goes to undefined state. In short, I want to control sda from code for some time, then i have to override the current sda value using test bench, and again after some time sda should get updated by the code. Is it possible to do this?