abhikohli said:Is it possible to do a complete latch based digital design for an ASIC ??
aniketd said:ya it's possible to design a latch based digital circuit
but from implementation point of view in FPGA or ASIC
timing analysis may be critical
chandhramohan said:Hi ,
Latch based designs give better timing & performance because of its clocking nature ,but the area overhead will be more.
Latch based LSSD design concept is propreitry of IBM & they had their own tools to handle it.Recently few of its tools are taken over by Cadence .The one I know is encounter test architect .
Regards
Chandhramohan
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