Is it possible to assign a value to a signal in a systemverilog assertion?

iammedjay said:

hi,

I have two sequences, s1 and s2. I have a property that checks these two sequences.
for example,

Code:

sequence s1 
req ##3 gnt;
endseqence

sequence s2
ack;
endsequence

Now I make use of a property for an assertion to check these two sequences.

Code:

property p1;
@(posedge clk) disable iff(reset)
s1 |-> s2;
endproperty

assert property (p1) else $warning("Assertion failed");

Once the property has been asserted successfully, is there a way where I can trigger a signal (say X) HIGH? I want it to trigger HIGH only when the property has been successfully asserted during the rest of the time, I want it to be LOW.

Any suggestions would be of great help, thank you.

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kripacharya said:

Surely there exists the equivalent of an IF-THEN-ELSE construct in whatever language you ainre using? That's programming 101.

I notice an 'iff' keyword.? ?

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kripacharya said:

I notice an 'iff' keyword.?

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